Commit ead99398 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'stm32-dt-for-v5.7-1' of... 

Merge tag 'stm32-dt-for-v5.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dt

STM32 DT updates for v5.3, round 1

Highlights:
----------

 - Add support for DH Electronics DHCOM SoM and PDK2 rev. 400 carrier
   board. It is based on stm32mp157c SoC.
 - Add OTG full support on stm32mp15.
 - Fix issues seen during yaml validation on stpmic and stmfx.
 - Add i2c power/wakeup support on stm32mp15.
 - Add card detect on sdcard on stm32mp boards

* tag 'stm32-dt-for-v5.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (25 commits)
  ARM: dts: stm32: use correct vqmmc regu for eMMC on stm32mp1 ED1/EV1 boards
  ARM: dts: stm32: add disable-wp property for SD-card on STM32MP1 boards
  ARM: dts: stm32: add cd-gpios properties for SD-cards on STM32MP1 boards
  ARM: dts: stm32: Do clean up in stmpic nodes on stm32mp15 boards
  ARM: dts: stm32: Rename stmfx joystick pins on stm32mp157c-ev1
  ARM: dts: stm32: add cpu clock-frequency property on stm32mp15x
  ARM: dts: stm32: add wakeup-source in all I2C nodes of stm32mp157c
  ARM: dts: stm32: add i2c4 sleep pinctrl on stm32mp157c-ed1
  ARM: dts: stm32: add i2c2/i2c5 sleep pinctrl on stm32mp157c-ev1
  ARM: dts: stm32: add i2c4 sleep pinctrl on stm32mp15xx-dkx
  ARM: dts: stm32: set i2c4 bus freq to 400KHz on stm32mp15 DK boards
  ARM: dts: stm32: set i2c4 bus freq to 400KHz on stm32mp157c-ed1
  ARM: dts: stm32: Correct stmfx node name on stm32mp157c-ev1 board
  ARM: dts: stm32: Correct stmfx node name on stm32746g-eval board
  ARM: dts: stm32: add resets property on all DMA nodes on stm32mp151
  ARM: dts: stm32: enable USB OTG Dual Role on stm32mp157c-ev1
  ARM: dts: stm32: add USB OTG pinctrl to stm32mp15
  ARM: dts: stm32: add USB OTG full support on stm32mp151
  ARM: dts: stm32: remove useless properties in stm32mp157a-avenger96 stmpic node
  ARM: dts: stm32: Add DH Electronics DHCOM STM32MP1 SoM and PDK2 board
  ...

Link: https://lore.kernel.org/r/ded09d01-df47-9572-4679-34669bff8916@st.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 25876536 431c89e6

arch/arm/boot/dts/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -1016,6 +1016,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ 
	stm32h743i-disco.dtb \

	stm32mp157a-avenger96.dtb \

	stm32mp157a-dk1.dtb \

	stm32mp157c-dhcom-pdk2.dtb \

	stm32mp157c-dk2.dtb \

	stm32mp157c-ed1.dtb \

	stm32mp157c-ev1.dtb

arch/arm/boot/dts/stm32746g-eval.dts

+1 −1
Original line number Diff line number Diff line
@@ -165,7 +165,7 @@ 
		interrupts = <8 IRQ_TYPE_EDGE_RISING>;

		interrupt-parent = <&gpioi>;



		stmfx_pinctrl: stmfx-pin-controller {

		stmfx_pinctrl: pinctrl {

			compatible = "st,stmfx-0300-pinctrl";

			gpio-controller;

			#gpio-cells = <2>;

arch/arm/boot/dts/stm32mp15-pinctrl.dtsi

+93 −0
Original line number Diff line number Diff line
@@ -162,6 +162,40 @@ 
		};

	};



	ethernet0_rmii_pins_a: rmii-0 {

		pins1 {

			pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */

				 <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */

				 <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */

				 <STM32_PINMUX('A', 1, AF0)>,   /* ETH1_RMII_REF_CLK */

				 <STM32_PINMUX('A', 2, AF11)>,  /* ETH1_MDIO */

				 <STM32_PINMUX('C', 1, AF11)>;  /* ETH1_MDC */

			bias-disable;

			drive-push-pull;

			slew-rate = <2>;

		};

		pins2 {

			pinmux = <STM32_PINMUX('C', 4, AF11)>,  /* ETH1_RMII_RXD0 */

				 <STM32_PINMUX('C', 5, AF11)>,  /* ETH1_RMII_RXD1 */

				 <STM32_PINMUX('A', 7, AF11)>;  /* ETH1_RMII_CRS_DV */

			bias-disable;

		};

	};



	ethernet0_rmii_pins_sleep_a: rmii-sleep-0 {

		pins1 {

			pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */

				 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */

				 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */

				 <STM32_PINMUX('A', 2, ANALOG)>,  /* ETH1_MDIO */

				 <STM32_PINMUX('C', 1, ANALOG)>,  /* ETH1_MDC */

				 <STM32_PINMUX('C', 4, ANALOG)>,  /* ETH1_RMII_RXD0 */

				 <STM32_PINMUX('C', 5, ANALOG)>,  /* ETH1_RMII_RXD1 */

				 <STM32_PINMUX('A', 1, ANALOG)>,  /* ETH1_RMII_REF_CLK */

				 <STM32_PINMUX('A', 7, ANALOG)>;  /* ETH1_RMII_CRS_DV */

		};

	};



	fmc_pins_a: fmc-0 {

		pins1 {

			pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
@@ -685,6 +719,26 @@ 
		};

	};





	sai2a_pins_b: sai2a-2 {

		pins1 {

			pinmux = <STM32_PINMUX('I', 6, AF10)>,	/* SAI2_SD_A */

				 <STM32_PINMUX('I', 7, AF10)>,	/* SAI2_FS_A */

				 <STM32_PINMUX('D', 13, AF10)>;	/* SAI2_SCK_A */

			slew-rate = <0>;

			drive-push-pull;

			bias-disable;

		};

	};



	sai2a_sleep_pins_b: sai2a-sleep-3 {

		pins {

			pinmux = <STM32_PINMUX('I', 6, ANALOG)>,  /* SAI2_SD_A */

				 <STM32_PINMUX('I', 7, ANALOG)>,  /* SAI2_FS_A */

				 <STM32_PINMUX('D', 13, ANALOG)>; /* SAI2_SCK_A */

		};

	};



	sai2b_pins_a: sai2b-0 {

		pins1 {

			pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */
@@ -1000,6 +1054,19 @@ 
		};

	};



	usart3_pins_a: usart3-0 {

		pins1 {

			pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */

			bias-disable;

			drive-push-pull;

			slew-rate = <0>;

		};

		pins2 {

			pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */

			bias-disable;

		};

	};



	uart4_pins_a: uart4-0 {

		pins1 {

			pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
@@ -1040,6 +1107,32 @@ 
			bias-disable;

		};

	};



	uart8_pins_a: uart8-0 {

		pins1 {

			pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */

			bias-disable;

			drive-push-pull;

			slew-rate = <0>;

		};

		pins2 {

			pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */

			bias-disable;

		};

	};



	usbotg_hs_pins_a: usbotg-hs-0 {

		pins {

			pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */

		};

	};



	usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 {

		pins {

			pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */

				 <STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */

		};

	};

};



&pinctrl_z {

arch/arm/boot/dts/stm32mp151.dtsi

+15 −1
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 


		cpu0: cpu@0 {

			compatible = "arm,cortex-a7";

			clock-frequency = <650000000>;

			device_type = "cpu";

			reg = <0>;

		};
@@ -483,6 +484,7 @@ 
			resets = <&rcc I2C1_R>;

			#address-cells = <1>;

			#size-cells = <0>;

			wakeup-source;

			status = "disabled";

		};
@@ -496,6 +498,7 @@ 
			resets = <&rcc I2C2_R>;

			#address-cells = <1>;

			#size-cells = <0>;

			wakeup-source;

			status = "disabled";

		};
@@ -509,6 +512,7 @@ 
			resets = <&rcc I2C3_R>;

			#address-cells = <1>;

			#size-cells = <0>;

			wakeup-source;

			status = "disabled";

		};
@@ -522,6 +526,7 @@ 
			resets = <&rcc I2C5_R>;

			#address-cells = <1>;

			#size-cells = <0>;

			wakeup-source;

			status = "disabled";

		};
@@ -959,6 +964,7 @@ 
				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&rcc DMA1>;

			resets = <&rcc DMA1_R>;

			#dma-cells = <4>;

			st,mem2mem;

			dma-requests = <8>;
@@ -976,6 +982,7 @@ 
				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&rcc DMA2>;

			resets = <&rcc DMA2_R>;

			#dma-cells = <4>;

			st,mem2mem;

			dma-requests = <8>;
@@ -989,6 +996,7 @@ 
			dma-masters = <&dma1 &dma2>;

			dma-channels = <16>;

			clocks = <&rcc DMAMUX>;

			resets = <&rcc DMAMUX_R>;

		};



		adc: adc@48003000 {
@@ -1044,7 +1052,7 @@ 
		};



		usbotg_hs: usb-otg@49000000 {

			compatible = "snps,dwc2";

			compatible = "st,stm32mp15-hsotg", "snps,dwc2";

			reg = <0x49000000 0x10000>;

			clocks = <&rcc USBO_K>;

			clock-names = "otg";
@@ -1055,6 +1063,7 @@ 
			g-np-tx-fifo-size = <32>;

			g-tx-fifo-size = <128 128 64 64 64 64 32 32>;

			dr_mode = "otg";

			usb33d-supply = <&usb33>;

			status = "disabled";

		};
@@ -1280,6 +1289,7 @@ 
			reg = <0x58000000 0x1000>;

			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&rcc MDMA>;

			resets = <&rcc MDMA_R>;

			#dma-cells = <5>;

			dma-channels = <32>;

			dma-requests = <48>;
@@ -1369,10 +1379,12 @@ 
			clock-names = "stmmaceth",

				      "mac-clk-tx",

				      "mac-clk-rx",

				      "eth-ck",

				      "ethstp";

			clocks = <&rcc ETHMAC>,

				 <&rcc ETHTX>,

				 <&rcc ETHRX>,

				 <&rcc ETHCK_K>,

				 <&rcc ETHSTP>;

			st,syscon = <&syscfg 0x4>;

			snps,mixed-burst;
@@ -1473,6 +1485,7 @@ 
			resets = <&rcc I2C4_R>;

			#address-cells = <1>;

			#size-cells = <0>;

			wakeup-source;

			status = "disabled";

		};
@@ -1508,6 +1521,7 @@ 
			resets = <&rcc I2C6_R>;

			#address-cells = <1>;

			#size-cells = <0>;

			wakeup-source;

			status = "disabled";

		};

arch/arm/boot/dts/stm32mp153.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ 
	cpus {

		cpu1: cpu@1 {

			compatible = "arm,cortex-a7";

			clock-frequency = <650000000>;

			device_type = "cpu";

			reg = <1>;

		};

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