Commit eac57949 authored by Steven King's avatar Steven King Committed by Greg Ungerer
Browse files

m68knommu: refactor Coldfire GPIO not to require GPIOLIB, eliminate mcf_gpio_chips. 



If we're not connecting external GPIO extenders via i2c or spi or whatever, we
probably don't need GPIOLIB.  If we provide an alternate implementation of
the GPIOLIB functions to use when only on-chip GPIO is needed, we can change
ARCH_REQUIRE_GPIOLIB to ARCH_WANTS_OPTIONAL_GPIOLIB so that GPIOLIB becomes
optional.

The downside is that in the GPIOLIB=n case, we lose all error checking done by
gpiolib, ie multiply allocating the gpio, free'ing gpio etc., so that the
only checking that can be done is if we reference a gpio on an external part.
Targets that need the extra error checking can still select GPIOLIB=y.

For the case where GPIOLIB=y, we can simplify the table of gpio chips to use a
single chip, eliminating the tables of chips in the 5xxx.c files.  The
original motivation for the definition of multiple chips was to match the way
many of the Coldfire variants defined their gpio as a spare array in memory.
However, all this really gains us is some error checking when we request a
gpio, gpiolib can check that it doesn't fall in one of the holes.  If thats
important, I think we can still come up with a better way of accomplishing
that.

Also in this patch is some general cleanup and reorganizing of the gpio header
files (I'm sure I must have had a reason why I sometimes used a prefix of
mcf_gpio and other times mcfgpio but for the life of me I can't think of it
now).

Signed-off-by: default avatarSteven King <sfking@fdwdc.com>
Signed-off-by: default avatarGreg Ungerer <gerg@uclinux.org>
parent 14be4252

arch/m68k/Kconfig.cpu

+1 −1
Original line number Diff line number Diff line
@@ -23,7 +23,7 @@ config M68KCLASSIC 
config COLDFIRE

	bool "Coldfire CPU family support"

	select GENERIC_GPIO

	select ARCH_REQUIRE_GPIOLIB

	select ARCH_WANT_OPTIONAL_GPIOLIB

	select ARCH_HAVE_CUSTOM_GPIO_H

	select CPU_HAS_NO_BITFIELDS

	select CPU_HAS_NO_MULDIV64

arch/m68k/include/asm/gpio.h

+4 −165
Original line number Diff line number Diff line
@@ -17,170 +17,9 @@ 
#define coldfire_gpio_h



#include <linux/io.h>

#include <asm-generic/gpio.h>

#include <asm/coldfire.h>

#include <asm/mcfsim.h>



/*

 * The Freescale Coldfire family is quite varied in how they implement GPIO.

 * Some parts have 8 bit ports, some have 16bit and some have 32bit; some have

 * only one port, others have multiple ports; some have a single data latch

 * for both input and output, others have a separate pin data register to read

 * input; some require a read-modify-write access to change an output, others

 * have set and clear registers for some of the outputs; Some have all the

 * GPIOs in a single control area, others have some GPIOs implemented in

 * different modules.

 *

 * This implementation attempts accommodate the differences while presenting

 * a generic interface that will optimize to as few instructions as possible.

 */

#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \

    defined(CONFIG_M520x) || defined(CONFIG_M523x) || \

    defined(CONFIG_M527x) || defined(CONFIG_M528x) || \

    defined(CONFIG_M532x) || defined(CONFIG_M54xx)



/* These parts have GPIO organized by 8 bit ports */



#define MCFGPIO_PORTTYPE		u8

#define MCFGPIO_PORTSIZE		8

#define mcfgpio_read(port)		__raw_readb(port)

#define mcfgpio_write(data, port)	__raw_writeb(data, port)



#elif defined(CONFIG_M5307) || defined(CONFIG_M5407) || defined(CONFIG_M5272)



/* These parts have GPIO organized by 16 bit ports */



#define MCFGPIO_PORTTYPE		u16

#define MCFGPIO_PORTSIZE		16

#define mcfgpio_read(port)		__raw_readw(port)

#define mcfgpio_write(data, port)	__raw_writew(data, port)



#elif defined(CONFIG_M5249)



/* These parts have GPIO organized by 32 bit ports */



#define MCFGPIO_PORTTYPE		u32

#define MCFGPIO_PORTSIZE		32

#define mcfgpio_read(port)		__raw_readl(port)

#define mcfgpio_write(data, port)	__raw_writel(data, port)



#endif



#define mcfgpio_bit(gpio)		(1 << ((gpio) %  MCFGPIO_PORTSIZE))

#define mcfgpio_port(gpio)		((gpio) / MCFGPIO_PORTSIZE)



#if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \

    defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)

/*

 * These parts have an 'Edge' Port module (external interrupt/GPIO) which uses

 * read-modify-write to change an output and a GPIO module which has separate

 * set/clr registers to directly change outputs with a single write access.

 */

#if defined(CONFIG_M528x)

/*

 * The 528x also has GPIOs in other modules (GPT, QADC) which use

 * read-modify-write as well as those controlled by the EPORT and GPIO modules.

 */

#define MCFGPIO_SCR_START		40

#else

#define MCFGPIO_SCR_START		8

#endif



#define MCFGPIO_SETR_PORT(gpio)		(MCFGPIO_SETR + \

					mcfgpio_port(gpio - MCFGPIO_SCR_START))



#define MCFGPIO_CLRR_PORT(gpio)		(MCFGPIO_CLRR + \

					mcfgpio_port(gpio - MCFGPIO_SCR_START))

#else



#define MCFGPIO_SCR_START		MCFGPIO_PIN_MAX

/* with MCFGPIO_SCR == MCFGPIO_PIN_MAX, these will be optimized away */

#define MCFGPIO_SETR_PORT(gpio)		0

#define MCFGPIO_CLRR_PORT(gpio)		0



#endif

/*

 * Coldfire specific helper functions

 */



/* return the port pin data register for a gpio */

static inline u32 __mcf_gpio_ppdr(unsigned gpio)

{

#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \

    defined(CONFIG_M5307) || defined(CONFIG_M5407)

	return MCFSIM_PADAT;

#elif defined(CONFIG_M5272)

	if (gpio < 16)

		return MCFSIM_PADAT;

	else if (gpio < 32)

		return MCFSIM_PBDAT;

	else

		return MCFSIM_PCDAT;

#elif defined(CONFIG_M5249)

	if (gpio < 32)

		return MCFSIM2_GPIOREAD;

	else

		return MCFSIM2_GPIO1READ;

#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \

      defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)

	if (gpio < 8)

		return MCFEPORT_EPPDR;

#if defined(CONFIG_M528x)

	else if (gpio < 16)

		return MCFGPTA_GPTPORT;

	else if (gpio < 24)

		return MCFGPTB_GPTPORT;

	else if (gpio < 32)

		return MCFQADC_PORTQA;

	else if (gpio < 40)

		return MCFQADC_PORTQB;

#endif

	else

		return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);

#else

	return 0;

#endif

}



/* return the port output data register for a gpio */

static inline u32 __mcf_gpio_podr(unsigned gpio)

{

#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \

    defined(CONFIG_M5307) || defined(CONFIG_M5407)

	return MCFSIM_PADAT;

#elif defined(CONFIG_M5272)

	if (gpio < 16)

		return MCFSIM_PADAT;

	else if (gpio < 32)

		return MCFSIM_PBDAT;

	else

		return MCFSIM_PCDAT;

#elif defined(CONFIG_M5249)

	if (gpio < 32)

		return MCFSIM2_GPIOWRITE;

	else

		return MCFSIM2_GPIO1WRITE;

#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \

      defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)

	if (gpio < 8)

		return MCFEPORT_EPDR;

#if defined(CONFIG_M528x)

	else if (gpio < 16)

		return MCFGPTA_GPTPORT;

	else if (gpio < 24)

		return MCFGPTB_GPTPORT;

	else if (gpio < 32)

		return MCFQADC_PORTQA;

	else if (gpio < 40)

		return MCFQADC_PORTQB;

#endif

	else

		return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);

#else

	return 0;

#endif

}



#include <asm/mcfgpio.h>

/*

 * The Generic GPIO functions

 *
@@ -191,7 +30,7 @@ static inline u32 __mcf_gpio_podr(unsigned gpio) 
static inline int gpio_get_value(unsigned gpio)

{

	if (__builtin_constant_p(gpio) && gpio < MCFGPIO_PIN_MAX)

		return mcfgpio_read(__mcf_gpio_ppdr(gpio)) & mcfgpio_bit(gpio);

		return mcfgpio_read(__mcfgpio_ppdr(gpio)) & mcfgpio_bit(gpio);

	else

		return __gpio_get_value(gpio);

}
@@ -204,12 +43,12 @@ static inline void gpio_set_value(unsigned gpio, int value) 
			MCFGPIO_PORTTYPE data;



			local_irq_save(flags);

			data = mcfgpio_read(__mcf_gpio_podr(gpio));

			data = mcfgpio_read(__mcfgpio_podr(gpio));

			if (value)

				data |= mcfgpio_bit(gpio);

			else

				data &= ~mcfgpio_bit(gpio);

			mcfgpio_write(data, __mcf_gpio_podr(gpio));

			mcfgpio_write(data, __mcfgpio_podr(gpio));

			local_irq_restore(flags);

		} else {

			if (value)

arch/m68k/include/asm/mcfgpio.h

+261 −68
Original line number Diff line number Diff line
@@ -16,82 +16,275 @@ 
#ifndef mcfgpio_h

#define mcfgpio_h



#include <linux/io.h>

#ifdef CONFIG_GPIOLIB

#include <asm-generic/gpio.h>

#else



int __mcfgpio_get_value(unsigned gpio);

void __mcfgpio_set_value(unsigned gpio, int value);

int __mcfgpio_direction_input(unsigned gpio);

int __mcfgpio_direction_output(unsigned gpio, int value);

int __mcfgpio_request(unsigned gpio);

void __mcfgpio_free(unsigned gpio);



/* our alternate 'gpiolib' functions */

static inline int __gpio_get_value(unsigned gpio)

{

	if (gpio < MCFGPIO_PIN_MAX)

		return __mcfgpio_get_value(gpio);

	else

		return -EINVAL;

}



static inline void __gpio_set_value(unsigned gpio, int value)

{

	if (gpio < MCFGPIO_PIN_MAX)

		__mcfgpio_set_value(gpio, value);

}



static inline int __gpio_cansleep(unsigned gpio)

{

	if (gpio < MCFGPIO_PIN_MAX)

		return 0;

	else

		return -EINVAL;

}



static inline int __gpio_to_irq(unsigned gpio)

{

	return -EINVAL;

}



static inline int gpio_direction_input(unsigned gpio)

{

	if (gpio < MCFGPIO_PIN_MAX)

		return __mcfgpio_direction_input(gpio);

	else

		return -EINVAL;

}



static inline int gpio_direction_output(unsigned gpio, int value)

{

	if (gpio < MCFGPIO_PIN_MAX)

		return __mcfgpio_direction_output(gpio, value);

	else

		return -EINVAL;

}



static inline int gpio_request(unsigned gpio, const char *label)

{

	if (gpio < MCFGPIO_PIN_MAX)

		return __mcfgpio_request(gpio);

	else

		return -EINVAL;

}



static inline void gpio_free(unsigned gpio)

{

	if (gpio < MCFGPIO_PIN_MAX)

		__mcfgpio_free(gpio);

}



#endif /* CONFIG_GPIOLIB */



struct mcf_gpio_chip {

	struct gpio_chip gpio_chip;

	void __iomem *pddr;

	void __iomem *podr;

	void __iomem *ppdr;

	void __iomem *setr;

	void __iomem *clrr;

	const u8 *gpio_to_pinmux;

};



extern struct mcf_gpio_chip mcf_gpio_chips[];

extern unsigned int mcf_gpio_chips_size;



int mcf_gpio_direction_input(struct gpio_chip *, unsigned);

int mcf_gpio_get_value(struct gpio_chip *, unsigned);

int mcf_gpio_direction_output(struct gpio_chip *, unsigned, int);

void mcf_gpio_set_value(struct gpio_chip *, unsigned, int);

void mcf_gpio_set_value_fast(struct gpio_chip *, unsigned, int);

int mcf_gpio_request(struct gpio_chip *, unsigned);

void mcf_gpio_free(struct gpio_chip *, unsigned);



/*

 *	Define macros to ease the pain of setting up the GPIO tables. There

 *	are two cases we need to deal with here, they cover all currently

 *	available ColdFire GPIO hardware. There are of course minor differences

 *	in the layout and number of bits in each ColdFire part, but the macros

 *	take all that in.

 * The Freescale Coldfire family is quite varied in how they implement GPIO.

 * Some parts have 8 bit ports, some have 16bit and some have 32bit; some have

 * only one port, others have multiple ports; some have a single data latch

 * for both input and output, others have a separate pin data register to read

 * input; some require a read-modify-write access to change an output, others

 * have set and clear registers for some of the outputs; Some have all the

 * GPIOs in a single control area, others have some GPIOs implemented in

 * different modules.

 *

 *	Firstly is the conventional GPIO registers where we toggle individual

 *	bits in a register, preserving the other bits in the register. For

 *	lack of a better term I have called this the slow method.

 * This implementation attempts accommodate the differences while presenting

 * a generic interface that will optimize to as few instructions as possible.

 */

#define	MCFGPS(mlabel, mbase, mngpio, mpddr, mpodr, mppdr)		    \

	{								    \

		.gpio_chip			= {			    \

			.label			= #mlabel,		    \

			.request		= mcf_gpio_request,	    \

			.free			= mcf_gpio_free,	    \

			.direction_input	= mcf_gpio_direction_input, \

			.direction_output	= mcf_gpio_direction_output,\

			.get			= mcf_gpio_get_value,	    \

			.set			= mcf_gpio_set_value,       \

			.base			= mbase,		    \

			.ngpio			= mngpio,		    \

		},							    \

		.pddr		= (void __iomem *) mpddr,		    \

		.podr		= (void __iomem *) mpodr,		    \

		.ppdr		= (void __iomem *) mppdr,		    \

	}

#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \

    defined(CONFIG_M520x) || defined(CONFIG_M523x) || \

    defined(CONFIG_M527x) || defined(CONFIG_M528x) || \

    defined(CONFIG_M532x) || defined(CONFIG_M54xx)



/* These parts have GPIO organized by 8 bit ports */



#define MCFGPIO_PORTTYPE		u8

#define MCFGPIO_PORTSIZE		8

#define mcfgpio_read(port)		__raw_readb(port)

#define mcfgpio_write(data, port)	__raw_writeb(data, port)



#elif defined(CONFIG_M5307) || defined(CONFIG_M5407) || defined(CONFIG_M5272)



/* These parts have GPIO organized by 16 bit ports */



#define MCFGPIO_PORTTYPE		u16

#define MCFGPIO_PORTSIZE		16

#define mcfgpio_read(port)		__raw_readw(port)

#define mcfgpio_write(data, port)	__raw_writew(data, port)



#elif defined(CONFIG_M5249)



/* These parts have GPIO organized by 32 bit ports */



#define MCFGPIO_PORTTYPE		u32

#define MCFGPIO_PORTSIZE		32

#define mcfgpio_read(port)		__raw_readl(port)

#define mcfgpio_write(data, port)	__raw_writel(data, port)



#endif



#define mcfgpio_bit(gpio)		(1 << ((gpio) %  MCFGPIO_PORTSIZE))

#define mcfgpio_port(gpio)		((gpio) / MCFGPIO_PORTSIZE)



#if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \

    defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)

/*

 * These parts have an 'Edge' Port module (external interrupt/GPIO) which uses

 * read-modify-write to change an output and a GPIO module which has separate

 * set/clr registers to directly change outputs with a single write access.

 */

#if defined(CONFIG_M528x)

/*

 *	Secondly is the faster case, where we have set and clear registers

 *	that allow us to set or clear a bit with a single write, not having

 *	to worry about preserving other bits.

 * The 528x also has GPIOs in other modules (GPT, QADC) which use

 * read-modify-write as well as those controlled by the EPORT and GPIO modules.

 */

#define	MCFGPF(mlabel, mbase, mngpio)					    \

	{								    \

		.gpio_chip			= {			    \

			.label			= #mlabel,		    \

			.request		= mcf_gpio_request,	    \

			.free			= mcf_gpio_free,	    \

			.direction_input	= mcf_gpio_direction_input, \

			.direction_output	= mcf_gpio_direction_output,\

			.get			= mcf_gpio_get_value,	    \

			.set			= mcf_gpio_set_value_fast,  \

			.base			= mbase,		    \

			.ngpio			= mngpio,		    \

		},							    \

		.pddr		= (void __iomem *) MCFGPIO_PDDR_##mlabel,   \

		.podr		= (void __iomem *) MCFGPIO_PODR_##mlabel,   \

		.ppdr		= (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \

		.setr		= (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \

		.clrr		= (void __iomem *) MCFGPIO_PCLRR_##mlabel,  \

#define MCFGPIO_SCR_START		40

#else

#define MCFGPIO_SCR_START		8

#endif



#define MCFGPIO_SETR_PORT(gpio)		(MCFGPIO_SETR + \

					mcfgpio_port(gpio - MCFGPIO_SCR_START))



#define MCFGPIO_CLRR_PORT(gpio)		(MCFGPIO_CLRR + \

					mcfgpio_port(gpio - MCFGPIO_SCR_START))

#else



#define MCFGPIO_SCR_START		MCFGPIO_PIN_MAX

/* with MCFGPIO_SCR == MCFGPIO_PIN_MAX, these will be optimized away */

#define MCFGPIO_SETR_PORT(gpio)		0

#define MCFGPIO_CLRR_PORT(gpio)		0



#endif

/*

 * Coldfire specific helper functions

 */



/* return the port pin data register for a gpio */

static inline u32 __mcfgpio_ppdr(unsigned gpio)

{

#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \

    defined(CONFIG_M5307) || defined(CONFIG_M5407)

	return MCFSIM_PADAT;

#elif defined(CONFIG_M5272)

	if (gpio < 16)

		return MCFSIM_PADAT;

	else if (gpio < 32)

		return MCFSIM_PBDAT;

	else

		return MCFSIM_PCDAT;

#elif defined(CONFIG_M5249)

	if (gpio < 32)

		return MCFSIM2_GPIOREAD;

	else

		return MCFSIM2_GPIO1READ;

#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \

      defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)

	if (gpio < 8)

		return MCFEPORT_EPPDR;

#if defined(CONFIG_M528x)

	else if (gpio < 16)

		return MCFGPTA_GPTPORT;

	else if (gpio < 24)

		return MCFGPTB_GPTPORT;

	else if (gpio < 32)

		return MCFQADC_PORTQA;

	else if (gpio < 40)

		return MCFQADC_PORTQB;

#endif

	else

		return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);

#else

	return 0;

#endif

}



/* return the port output data register for a gpio */

static inline u32 __mcfgpio_podr(unsigned gpio)

{

#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \

    defined(CONFIG_M5307) || defined(CONFIG_M5407)

	return MCFSIM_PADAT;

#elif defined(CONFIG_M5272)

	if (gpio < 16)

		return MCFSIM_PADAT;

	else if (gpio < 32)

		return MCFSIM_PBDAT;

	else

		return MCFSIM_PCDAT;

#elif defined(CONFIG_M5249)

	if (gpio < 32)

		return MCFSIM2_GPIOWRITE;

	else

		return MCFSIM2_GPIO1WRITE;

#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \

      defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)

	if (gpio < 8)

		return MCFEPORT_EPDR;

#if defined(CONFIG_M528x)

	else if (gpio < 16)

		return MCFGPTA_GPTPORT;

	else if (gpio < 24)

		return MCFGPTB_GPTPORT;

	else if (gpio < 32)

		return MCFQADC_PORTQA;

	else if (gpio < 40)

		return MCFQADC_PORTQB;

#endif

	else

		return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);

#else

	return 0;

#endif

}



/* return the port direction data register for a gpio */

static inline u32 __mcfgpio_pddr(unsigned gpio)

{

#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \

    defined(CONFIG_M5307) || defined(CONFIG_M5407)

	return MCFSIM_PADDR;

#elif defined(CONFIG_M5272)

	if (gpio < 16)

		return MCFSIM_PADDR;

	else if (gpio < 32)

		return MCFSIM_PBDDR;

	else

		return MCFSIM_PCDDR;

#elif defined(CONFIG_M5249)

	if (gpio < 32)

		return MCFSIM2_GPIOENABLE;

	else

		return MCFSIM2_GPIO1ENABLE;

#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \

      defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)

	if (gpio < 8)

		return MCFEPORT_EPDDR;

#if defined(CONFIG_M528x)

	else if (gpio < 16)

		return MCFGPTA_GPTDDR;

	else if (gpio < 24)

		return MCFGPTB_GPTDDR;

	else if (gpio < 32)

		return MCFQADC_DDRQA;

	else if (gpio < 40)

		return MCFQADC_DDRQB;

#endif

	else

		return MCFGPIO_PDDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);

#else

	return 0;

#endif

}



#endif /* mcfgpio_h */

arch/m68k/include/asm/pinmux.h

deleted100644 → 0
+0 −30
Original line number Diff line number Diff line 
/*

 * Coldfire generic GPIO pinmux support.

 *

 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; version 2 of the License.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef pinmux_h

#define pinmux_h



#define MCFPINMUX_NONE		-1



extern int mcf_pinmux_request(unsigned, unsigned);

extern void mcf_pinmux_release(unsigned, unsigned);



static inline int mcf_pinmux_is_valid(unsigned pinmux)

{

	return pinmux != MCFPINMUX_NONE;

}



#endif

arch/m68k/platform/coldfire/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -32,5 +32,5 @@ obj-$(CONFIG_NETtel) += nettel.o 
obj-$(CONFIG_CLEOPATRA)	+= nettel.o

obj-$(CONFIG_FIREBEE)	+= firebee.o



obj-y			+= pinmux.o gpio.o

obj-y			+= gpio.o

extra-y := head.o

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