Commit eab35405 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 

Pull ARM SoC-related driver updates from Olof Johansson:
 "Various driver updates for platforms:

   - Nvidia: Fuse support for Tegra194, continued memory controller
     pieces for Tegra30

   - NXP/FSL: Refactorings of QuickEngine drivers to support
     ARM/ARM64/PPC

   - NXP/FSL: i.MX8MP SoC driver pieces

   - TI Keystone: ring accelerator driver

   - Qualcomm: SCM driver cleanup/refactoring + support for new SoCs.

   - Xilinx ZynqMP: feature checking interface for firmware. Mailbox
     communication for power management

   - Overall support patch set for cpuidle on more complex hierarchies
     (PSCI-based)

  and misc cleanups, refactorings of Marvell, TI, other platforms"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (166 commits)
  drivers: soc: xilinx: Use mailbox IPI callback
  dt-bindings: power: reset: xilinx: Add bindings for ipi mailbox
  drivers: soc: ti: knav_qmss_queue: Pass lockdep expression to RCU lists
  MAINTAINERS: Add brcmstb PCIe controller entry
  soc/tegra: fuse: Unmap registers once they are not needed anymore
  soc/tegra: fuse: Correct straps' address for older Tegra124 device trees
  soc/tegra: fuse: Warn if straps are not ready
  soc/tegra: fuse: Cache values of straps and Chip ID registers
  memory: tegra30-emc: Correct error message for timed out auto calibration
  memory: tegra30-emc: Firm up hardware programming sequence
  memory: tegra30-emc: Firm up suspend/resume sequence
  soc/tegra: regulators: Do nothing if voltage is unchanged
  memory: tegra: Correct reset value of xusb_hostr
  soc/tegra: fuse: Add APB DMA dependency for Tegra20
  bus: tegra-aconnect: Remove PM_CLK dependency
  dt-bindings: mediatek: add MT6765 power dt-bindings
  soc: mediatek: cmdq: delete not used define
  memory: tegra: Add support for the Tegra194 memory controller
  memory: tegra: Only include support for enabled SoCs
  memory: tegra: Support DVFS on Tegra186 and later
  ...
parents 1afa9c3b 88b47501

Documentation/devicetree/bindings/arm/cpus.yaml

+15 −0
Original line number Diff line number Diff line
@@ -242,6 +242,21 @@ properties: 


      where voltage is in V, frequency is in MHz.



  power-domains:

    $ref: '/schemas/types.yaml#/definitions/phandle-array'

    description:

      List of phandles and PM domain specifiers, as defined by bindings of the

      PM domain provider (see also ../power_domain.txt).



  power-domain-names:

    $ref: '/schemas/types.yaml#/definitions/string-array'

    description:

      A list of power domain name strings sorted in the same order as the

      power-domains property.



      For PSCI based platforms, the name corresponding to the index of the PSCI

      PM domain provider, must be "psci".



  qcom,saw:

    $ref: '/schemas/types.yaml#/definitions/phandle'

    description: |

Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml

+1 −1
Original line number Diff line number Diff line
@@ -47,7 +47,7 @@ examples: 
  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    cache-controller@1100000 {

    system-cache-controller@1100000 {

      compatible = "qcom,sdm845-llcc";

      reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;

      reg-names = "llcc_base", "llcc_broadcast_base";

Documentation/devicetree/bindings/arm/psci.yaml

+104 −0
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@@ -102,6 +102,34 @@ properties: 
      [1] Kernel documentation - ARM idle states bindings

        Documentation/devicetree/bindings/arm/idle-states.txt



  "#power-domain-cells":

    description:

      The number of cells in a PM domain specifier as per binding in [3].

      Must be 0 as to represent a single PM domain.



      ARM systems can have multiple cores, sometimes in an hierarchical

      arrangement. This often, but not always, maps directly to the processor

      power topology of the system. Individual nodes in a topology have their

      own specific power states and can be better represented hierarchically.



      For these cases, the definitions of the idle states for the CPUs and the

      CPU topology, must conform to the binding in [3]. The idle states

      themselves must conform to the binding in [4] and must specify the

      arm,psci-suspend-param property.



      It should also be noted that, in PSCI firmware v1.0 the OS-Initiated

      (OSI) CPU suspend mode is introduced. Using a hierarchical representation

      helps to implement support for OSI mode and OS implementations may choose

      to mandate it.



      [3] Documentation/devicetree/bindings/power/power_domain.txt

      [4] Documentation/devicetree/bindings/power/domain-idle-state.txt



  power-domains:

    $ref: '/schemas/types.yaml#/definitions/phandle-array'

    description:

      List of phandles and PM domain specifiers, as defined by bindings of the

      PM domain provider.



required:

  - compatible
@@ -160,4 +188,80 @@ examples: 
      cpu_on = <0x95c10002>;

      cpu_off = <0x95c10001>;

    };



  - |+



    // Case 4: CPUs and CPU idle states described using the hierarchical model.



    cpus {

      #size-cells = <0>;

      #address-cells = <1>;



      CPU0: cpu@0 {

        device_type = "cpu";

        compatible = "arm,cortex-a53", "arm,armv8";

        reg = <0x0>;

        enable-method = "psci";

        power-domains = <&CPU_PD0>;

        power-domain-names = "psci";

      };



      CPU1: cpu@1 {

        device_type = "cpu";

        compatible = "arm,cortex-a57", "arm,armv8";

        reg = <0x100>;

        enable-method = "psci";

        power-domains = <&CPU_PD1>;

        power-domain-names = "psci";

      };



      idle-states {



        CPU_PWRDN: cpu-power-down {

          compatible = "arm,idle-state";

          arm,psci-suspend-param = <0x0000001>;

          entry-latency-us = <10>;

          exit-latency-us = <10>;

          min-residency-us = <100>;

        };



        CLUSTER_RET: cluster-retention {

          compatible = "domain-idle-state";

          arm,psci-suspend-param = <0x1000011>;

          entry-latency-us = <500>;

          exit-latency-us = <500>;

          min-residency-us = <2000>;

        };



        CLUSTER_PWRDN: cluster-power-down {

          compatible = "domain-idle-state";

          arm,psci-suspend-param = <0x1000031>;

          entry-latency-us = <2000>;

          exit-latency-us = <2000>;

          min-residency-us = <6000>;

        };

      };

    };



    psci {

      compatible = "arm,psci-1.0";

      method = "smc";



      CPU_PD0: cpu-pd0 {

        #power-domain-cells = <0>;

        domain-idle-states = <&CPU_PWRDN>;

        power-domains = <&CLUSTER_PD>;

      };



      CPU_PD1: cpu-pd1 {

        #power-domain-cells = <0>;

        domain-idle-states =  <&CPU_PWRDN>;

        power-domains = <&CLUSTER_PD>;

      };



      CLUSTER_PD: cluster-pd {

        #power-domain-cells = <0>;

        domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;

      };

    };

...

Documentation/devicetree/bindings/power/qcom,rpmpd.txt

deleted100644 → 0
+0 −148
Original line number Diff line number Diff line 
Qualcomm RPM/RPMh Power domains



For RPM/RPMh Power domains, we communicate a performance state to RPM/RPMh

which then translates it into a corresponding voltage on a rail



Required Properties:

 - compatible: Should be one of the following

	* qcom,msm8976-rpmpd: RPM Power domain for the msm8976 family of SoC

	* qcom,msm8996-rpmpd: RPM Power domain for the msm8996 family of SoC

	* qcom,msm8998-rpmpd: RPM Power domain for the msm8998 family of SoC

	* qcom,qcs404-rpmpd: RPM Power domain for the qcs404 family of SoC

	* qcom,sdm845-rpmhpd: RPMh Power domain for the sdm845 family of SoC

 - #power-domain-cells: number of cells in Power domain specifier

	must be 1.

 - operating-points-v2: Phandle to the OPP table for the Power domain.

	Refer to Documentation/devicetree/bindings/power/power_domain.txt

	and Documentation/devicetree/bindings/opp/opp.txt for more details



Refer to <dt-bindings/power/qcom-rpmpd.h> for the level values for

various OPPs for different platforms as well as Power domain indexes



Example: rpmh power domain controller and OPP table



#include <dt-bindings/power/qcom-rpmhpd.h>



opp-level values specified in the OPP tables for RPMh power domains

should use the RPMH_REGULATOR_LEVEL_* constants from

<dt-bindings/power/qcom-rpmhpd.h>



	rpmhpd: power-controller {

		compatible = "qcom,sdm845-rpmhpd";

		#power-domain-cells = <1>;

		operating-points-v2 = <&rpmhpd_opp_table>;



		rpmhpd_opp_table: opp-table {

			compatible = "operating-points-v2";



			rpmhpd_opp_ret: opp1 {

				opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;

			};



			rpmhpd_opp_min_svs: opp2 {

				opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;

			};



			rpmhpd_opp_low_svs: opp3 {

				opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;

			};



			rpmhpd_opp_svs: opp4 {

				opp-level = <RPMH_REGULATOR_LEVEL_SVS>;

			};



			rpmhpd_opp_svs_l1: opp5 {

				opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;

			};



			rpmhpd_opp_nom: opp6 {

				opp-level = <RPMH_REGULATOR_LEVEL_NOM>;

			};



			rpmhpd_opp_nom_l1: opp7 {

				opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;

			};



			rpmhpd_opp_nom_l2: opp8 {

				opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;

			};



			rpmhpd_opp_turbo: opp9 {

				opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;

			};



			rpmhpd_opp_turbo_l1: opp10 {

				opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;

			};

		};

	};



Example: rpm power domain controller and OPP table



	rpmpd: power-controller {

		compatible = "qcom,msm8996-rpmpd";

		#power-domain-cells = <1>;

		operating-points-v2 = <&rpmpd_opp_table>;



		rpmpd_opp_table: opp-table {

			compatible = "operating-points-v2";



			rpmpd_opp_low: opp1 {

				opp-level = <1>;

			};



			rpmpd_opp_ret: opp2 {

				opp-level = <2>;

			};



			rpmpd_opp_svs: opp3 {

				opp-level = <3>;

			};



			rpmpd_opp_normal: opp4 {

				opp-level = <4>;

			};



			rpmpd_opp_high: opp5 {

				opp-level = <5>;

			};



			rpmpd_opp_turbo: opp6 {

				opp-level = <6>;

			};

		};

	};



Example: Client/Consumer device using OPP table



	leaky-device0@12350000 {

		compatible = "foo,i-leak-current";

		reg = <0x12350000 0x1000>;

		power-domains = <&rpmhpd SDM845_MX>;

		operating-points-v2 = <&leaky_opp_table>;

	};





	leaky_opp_table: opp-table {

		compatible = "operating-points-v2";



		opp1 {

			opp-hz = /bits/ 64 <144000>;

			required-opps = <&rpmhpd_opp_low>;

		};



		opp2 {

			opp-hz = /bits/ 64 <400000>;

			required-opps = <&rpmhpd_opp_ret>;

		};



		opp3 {

			opp-hz = /bits/ 64 <20000000>;

			required-opps = <&rpmpd_opp_svs>;

		};



		opp4 {

			opp-hz = /bits/ 64 <25000000>;

			required-opps = <&rpmpd_opp_normal>;

		};

	};

Documentation/devicetree/bindings/power/qcom,rpmpd.yaml

0 → 100644
+170 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/power/qcom,rpmpd.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm RPM/RPMh Power domains



maintainers:

  - Rajendra Nayak <rnayak@codeaurora.org>



description:

  For RPM/RPMh Power domains, we communicate a performance state to RPM/RPMh

  which then translates it into a corresponding voltage on a rail.



properties:

  compatible:

    enum:

      - qcom,msm8976-rpmpd

      - qcom,msm8996-rpmpd

      - qcom,msm8998-rpmpd

      - qcom,qcs404-rpmpd

      - qcom,sc7180-rpmhpd

      - qcom,sdm845-rpmhpd

      - qcom,sm8150-rpmhpd



  '#power-domain-cells':

    const: 1



  operating-points-v2: true



  opp-table:

    type: object



required:

  - compatible

  - '#power-domain-cells'

  - operating-points-v2



additionalProperties: false



examples:

  - |



    // Example 1 (rpmh power domain controller and OPP table):



    #include <dt-bindings/power/qcom-rpmpd.h>



    rpmhpd: power-controller {

      compatible = "qcom,sdm845-rpmhpd";

      #power-domain-cells = <1>;

      operating-points-v2 = <&rpmhpd_opp_table>;



      rpmhpd_opp_table: opp-table {

        compatible = "operating-points-v2";



        rpmhpd_opp_ret: opp1 {

          opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;

        };



        rpmhpd_opp_min_svs: opp2 {

          opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;

        };



        rpmhpd_opp_low_svs: opp3 {

          opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;

        };



        rpmhpd_opp_svs: opp4 {

          opp-level = <RPMH_REGULATOR_LEVEL_SVS>;

        };



        rpmhpd_opp_svs_l1: opp5 {

          opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;

        };



        rpmhpd_opp_nom: opp6 {

          opp-level = <RPMH_REGULATOR_LEVEL_NOM>;

        };



        rpmhpd_opp_nom_l1: opp7 {

          opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;

        };



        rpmhpd_opp_nom_l2: opp8 {

          opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;

        };



        rpmhpd_opp_turbo: opp9 {

          opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;

        };



        rpmhpd_opp_turbo_l1: opp10 {

          opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;

        };

      };

    };



  - |



    // Example 2 (rpm power domain controller and OPP table):



    rpmpd: power-controller {

      compatible = "qcom,msm8996-rpmpd";

      #power-domain-cells = <1>;

      operating-points-v2 = <&rpmpd_opp_table>;



      rpmpd_opp_table: opp-table {

        compatible = "operating-points-v2";



        rpmpd_opp_low: opp1 {

          opp-level = <1>;

        };



        rpmpd_opp_ret: opp2 {

          opp-level = <2>;

        };



        rpmpd_opp_svs: opp3 {

          opp-level = <3>;

        };



        rpmpd_opp_normal: opp4 {

          opp-level = <4>;

        };



        rpmpd_opp_high: opp5 {

          opp-level = <5>;

        };



        rpmpd_opp_turbo: opp6 {

          opp-level = <6>;

        };

      };

    };



  - |



    // Example 3 (Client/Consumer device using OPP table):



    leaky-device0@12350000 {

      compatible = "foo,i-leak-current";

      reg = <0x12350000 0x1000>;

      power-domains = <&rpmhpd 0>;

      operating-points-v2 = <&leaky_opp_table>;

    };



    leaky_opp_table: opp-table {

      compatible = "operating-points-v2";

      opp1 {

        opp-hz = /bits/ 64 <144000>;

        required-opps = <&rpmhpd_opp_low>;

      };



      opp2 {

        opp-hz = /bits/ 64 <400000>;

        required-opps = <&rpmhpd_opp_ret>;

      };



      opp3 {

        opp-hz = /bits/ 64 <20000000>;

        required-opps = <&rpmpd_opp_svs>;

      };



      opp4 {

        opp-hz = /bits/ 64 <25000000>;

        required-opps = <&rpmpd_opp_normal>;

      };

    };

...

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