Merge tag 'v4.5-rockchip-clk1_1' of... (eaaa6fb5) · Commits · 戴 / test

Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt

0 → 100644

+56 −0

Original line number	Diff line number	Diff line
		* Rockchip RK3036 Clock and Reset Unit

		The RK3036 clock controller generates and supplies clock to various
		controllers within the SoC and also implements a reset controller for SoC
		peripherals.

		Required Properties:

		- compatible: should be "rockchip,rk3036-cru"
		- reg: physical base address of the controller and length of memory mapped
		region.
		- #clock-cells: should be 1.
		- #reset-cells: should be 1.

		Optional Properties:

		- rockchip,grf: phandle to the syscon managing the "general register files"
		If missing pll rates are not changeable, due to the missing pll lock status.

		Each clock is assigned an identifier and client nodes can use this identifier
		to specify the clock which they consume. All available clocks are defined as
		preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be
		used in device tree sources. Similar macros exist for the reset sources in
		these files.

		External clocks:

		There are several clocks that are generated outside the SoC. It is expected
		that they are defined using standard clock bindings with following
		clock-output-names:
		- "xin24m" - crystal input - required,
		- "ext_i2s" - external I2S clock - optional,
		- "ext_gmac" - external GMAC clock - optional

		Example: Clock controller node:

		cru: cru@20000000 {
		compatible = "rockchip,rk3036-cru";
		reg = <0x20000000 0x1000>;
		rockchip,grf = <&grf>;

		#clock-cells = <1>;
		#reset-cells = <1>;
		};

		Example: UART controller node that consumes the clock generated by the clock
		controller:

		uart0: serial@20060000 {
		compatible = "snps,dw-apb-uart";
		reg = <0x20060000 0x100>;
		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
		clocks = <&cru SCLK_UART0>;
		};

Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt

0 → 100644

+58 −0

Original line number	Diff line number	Diff line
		* Rockchip RK3228 Clock and Reset Unit

		The RK3228 clock controller generates and supplies clock to various
		controllers within the SoC and also implements a reset controller for SoC
		peripherals.

		Required Properties:

		- compatible: should be "rockchip,rk3228-cru"
		- reg: physical base address of the controller and length of memory mapped
		region.
		- #clock-cells: should be 1.
		- #reset-cells: should be 1.

		Optional Properties:

		- rockchip,grf: phandle to the syscon managing the "general register files"
		If missing pll rates are not changeable, due to the missing pll lock status.

		Each clock is assigned an identifier and client nodes can use this identifier
		to specify the clock which they consume. All available clocks are defined as
		preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be
		used in device tree sources. Similar macros exist for the reset sources in
		these files.

		External clocks:

		There are several clocks that are generated outside the SoC. It is expected
		that they are defined using standard clock bindings with following
		clock-output-names:
		- "xin24m" - crystal input - required,
		- "ext_i2s" - external I2S clock - optional,
		- "ext_gmac" - external GMAC clock - optional
		- "ext_hsadc" - external HSADC clock - optional
		- "phy_50m_out" - output clock of the pll in the mac phy

		Example: Clock controller node:

		cru: cru@20000000 {
		compatible = "rockchip,rk3228-cru";
		reg = <0x20000000 0x1000>;
		rockchip,grf = <&grf>;

		#clock-cells = <1>;
		#reset-cells = <1>;
		};

		Example: UART controller node that consumes the clock generated by the clock
		controller:

		uart0: serial@10110000 {
		compatible = "snps,dw-apb-uart";
		reg = <0x10110000 0x100>;
		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
		clocks = <&cru SCLK_UART0>;
		};

drivers/clk/rockchip/Makefile

+2 −0

Original line number	Diff line number	Diff line
		@@ -10,6 +10,8 @@ obj-y += clk-inverter.o
		obj-y += clk-mmc-phase.o
		obj-$(CONFIG_RESET_CONTROLLER) += softrst.o

		obj-y += clk-rk3036.o
		obj-y += clk-rk3188.o
		obj-y += clk-rk3228.o
		obj-y += clk-rk3288.o
		obj-y += clk-rk3368.o

drivers/clk/rockchip/clk-cpu.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -242,8 +242,8 @@ struct clk rockchip_clk_register_cpuclk(const char name,
		struct clk clk, cclk;
		int ret;

		if (num_parents != 2) {
		pr_err("%s: needs two parent clocks\n", __func__);
		if (num_parents < 2) {
		pr_err("%s: needs at least two parent clocks\n", __func__);
		return ERR_PTR(-EINVAL);
		}

drivers/clk/rockchip/clk-pll.c

+257 −1

Original line number	Diff line number	Diff line
		@@ -2,6 +2,9 @@
		* Copyright (c) 2014 MundoReader S.L.
		* Author: Heiko Stuebner <heiko@sntech.de>
		*
		* Copyright (c) 2015 Rockchip Electronics Co. Ltd.
		* Author: Xing Zheng <zhengxing@rock-chips.com>
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License as published by
		* the Free Software Foundation; either version 2 of the License, or
		@@ -19,6 +22,7 @@
		#include <linux/delay.h>
		#include <linux/clk-provider.h>
		#include <linux/regmap.h>
		#include <linux/clk.h>
		#include "clk.h"

		#define PLL_MODE_MASK 0x3
		@@ -107,6 +111,252 @@ static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)
		return -ETIMEDOUT;
		}

		/**
		* PLL used in RK3036
		*/

		#define RK3036_PLLCON(i) (i * 0x4)
		#define RK3036_PLLCON0_FBDIV_MASK 0xfff
		#define RK3036_PLLCON0_FBDIV_SHIFT 0
		#define RK3036_PLLCON0_POSTDIV1_MASK 0x7
		#define RK3036_PLLCON0_POSTDIV1_SHIFT 12
		#define RK3036_PLLCON1_REFDIV_MASK 0x3f
		#define RK3036_PLLCON1_REFDIV_SHIFT 0
		#define RK3036_PLLCON1_POSTDIV2_MASK 0x7
		#define RK3036_PLLCON1_POSTDIV2_SHIFT 6
		#define RK3036_PLLCON1_DSMPD_MASK 0x1
		#define RK3036_PLLCON1_DSMPD_SHIFT 12
		#define RK3036_PLLCON2_FRAC_MASK 0xffffff
		#define RK3036_PLLCON2_FRAC_SHIFT 0

		#define RK3036_PLLCON1_PWRDOWN (1 << 13)

		static void rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll,
		struct rockchip_pll_rate_table *rate)
		{
		u32 pllcon;

		pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0));
		rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT)
		& RK3036_PLLCON0_FBDIV_MASK);
		rate->postdiv1 = ((pllcon >> RK3036_PLLCON0_POSTDIV1_SHIFT)
		& RK3036_PLLCON0_POSTDIV1_MASK);

		pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1));
		rate->refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT)
		& RK3036_PLLCON1_REFDIV_MASK);
		rate->postdiv2 = ((pllcon >> RK3036_PLLCON1_POSTDIV2_SHIFT)
		& RK3036_PLLCON1_POSTDIV2_MASK);
		rate->dsmpd = ((pllcon >> RK3036_PLLCON1_DSMPD_SHIFT)
		& RK3036_PLLCON1_DSMPD_MASK);

		pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
		rate->frac = ((pllcon >> RK3036_PLLCON2_FRAC_SHIFT)
		& RK3036_PLLCON2_FRAC_MASK);
		}

		static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw,
		unsigned long prate)
		{
		struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
		struct rockchip_pll_rate_table cur;
		u64 rate64 = prate;

		rockchip_rk3036_pll_get_params(pll, &cur);

		rate64 *= cur.fbdiv;
		do_div(rate64, cur.refdiv);

		if (cur.dsmpd == 0) {
		/* fractional mode */
		u64 frac_rate64 = prate * cur.frac;

		do_div(frac_rate64, cur.refdiv);
		rate64 += frac_rate64 >> 24;
		}

		do_div(rate64, cur.postdiv1);
		do_div(rate64, cur.postdiv2);

		return (unsigned long)rate64;
		}

		static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll,
		const struct rockchip_pll_rate_table *rate)
		{
		const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
		struct clk_mux *pll_mux = &pll->pll_mux;
		struct rockchip_pll_rate_table cur;
		u32 pllcon;
		int rate_change_remuxed = 0;
		int cur_parent;
		int ret;

		pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
		__func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv,
		rate->postdiv2, rate->dsmpd, rate->frac);

		rockchip_rk3036_pll_get_params(pll, &cur);
		cur.rate = 0;

		cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
		if (cur_parent == PLL_MODE_NORM) {
		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
		rate_change_remuxed = 1;
		}

		/* update pll values */
		writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK,
		RK3036_PLLCON0_FBDIV_SHIFT) \|
		HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK,
		RK3036_PLLCON0_POSTDIV1_SHIFT),
		pll->reg_base + RK3036_PLLCON(0));

		writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK,
		RK3036_PLLCON1_REFDIV_SHIFT) \|
		HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK,
		RK3036_PLLCON1_POSTDIV2_SHIFT) \|
		HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK,
		RK3036_PLLCON1_DSMPD_SHIFT),
		pll->reg_base + RK3036_PLLCON(1));

		/* GPLL CON2 is not HIWORD_MASK */
		pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
		pllcon &= ~(RK3036_PLLCON2_FRAC_MASK << RK3036_PLLCON2_FRAC_SHIFT);
		pllcon \|= rate->frac << RK3036_PLLCON2_FRAC_SHIFT;
		writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2));

		/* wait for the pll to lock */
		ret = rockchip_pll_wait_lock(pll);
		if (ret) {
		pr_warn("%s: pll update unsucessful, trying to restore old params\n",
		__func__);
		rockchip_rk3036_pll_set_params(pll, &cur);
		}

		if (rate_change_remuxed)
		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);

		return ret;
		}

		static int rockchip_rk3036_pll_set_rate(struct clk_hw *hw, unsigned long drate,
		unsigned long prate)
		{
		struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
		const struct rockchip_pll_rate_table *rate;
		unsigned long old_rate = rockchip_rk3036_pll_recalc_rate(hw, prate);
		struct regmap *grf = rockchip_clk_get_grf();

		if (IS_ERR(grf)) {
		pr_debug("%s: grf regmap not available, aborting rate change\n",
		__func__);
		return PTR_ERR(grf);
		}

		pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n",
		__func__, __clk_get_name(hw->clk), old_rate, drate, prate);

		/* Get required rate settings from table */
		rate = rockchip_get_pll_settings(pll, drate);
		if (!rate) {
		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
		drate, __clk_get_name(hw->clk));
		return -EINVAL;
		}

		return rockchip_rk3036_pll_set_params(pll, rate);
		}

		static int rockchip_rk3036_pll_enable(struct clk_hw *hw)
		{
		struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);

		writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0),
		pll->reg_base + RK3036_PLLCON(1));

		return 0;
		}

		static void rockchip_rk3036_pll_disable(struct clk_hw *hw)
		{
		struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);

		writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN,
		RK3036_PLLCON1_PWRDOWN, 0),
		pll->reg_base + RK3036_PLLCON(1));
		}

		static int rockchip_rk3036_pll_is_enabled(struct clk_hw *hw)
		{
		struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
		u32 pllcon = readl(pll->reg_base + RK3036_PLLCON(1));

		return !(pllcon & RK3036_PLLCON1_PWRDOWN);
		}

		static void rockchip_rk3036_pll_init(struct clk_hw *hw)
		{
		struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
		const struct rockchip_pll_rate_table *rate;
		struct rockchip_pll_rate_table cur;
		unsigned long drate;

		if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
		return;

		drate = clk_hw_get_rate(hw);
		rate = rockchip_get_pll_settings(pll, drate);

		/* when no rate setting for the current rate, rely on clk_set_rate */
		if (!rate)
		return;

		rockchip_rk3036_pll_get_params(pll, &cur);

		pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk),
		drate);
		pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
		cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2,
		cur.dsmpd, cur.frac);
		pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
		rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2,
		rate->dsmpd, rate->frac);

		if (rate->fbdiv != cur.fbdiv \|\| rate->postdiv1 != cur.postdiv1 \|\|
		rate->refdiv != cur.refdiv \|\| rate->postdiv2 != cur.postdiv2 \|\|
		rate->dsmpd != cur.dsmpd \|\| rate->frac != cur.frac) {
		struct clk *parent = clk_get_parent(hw->clk);

		if (!parent) {
		pr_warn("%s: parent of %s not available\n",
		__func__, __clk_get_name(hw->clk));
		return;
		}

		pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
		__func__, __clk_get_name(hw->clk));
		rockchip_rk3036_pll_set_params(pll, rate);
		}
		}

		static const struct clk_ops rockchip_rk3036_pll_clk_norate_ops = {
		.recalc_rate = rockchip_rk3036_pll_recalc_rate,
		.enable = rockchip_rk3036_pll_enable,
		.disable = rockchip_rk3036_pll_disable,
		.is_enabled = rockchip_rk3036_pll_is_enabled,
		};

		static const struct clk_ops rockchip_rk3036_pll_clk_ops = {
		.recalc_rate = rockchip_rk3036_pll_recalc_rate,
		.round_rate = rockchip_pll_round_rate,
		.set_rate = rockchip_rk3036_pll_set_rate,
		.enable = rockchip_rk3036_pll_enable,
		.disable = rockchip_rk3036_pll_disable,
		.is_enabled = rockchip_rk3036_pll_is_enabled,
		.init = rockchip_rk3036_pll_init,
		};

		/**
		* PLL used in RK3066, RK3188 and RK3288
		*/
		@@ -376,7 +626,7 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
		pll_mux->lock = lock;
		pll_mux->hw.init = &init;

		if (pll_type == pll_rk3066)
		if (pll_type == pll_rk3036 \|\| pll_type == pll_rk3066)
		pll_mux->flags \|= CLK_MUX_HIWORD_MASK;

		/* the actual muxing is xin24m, pll-output, xin32k */
		@@ -421,6 +671,12 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
		}

		switch (pll_type) {
		case pll_rk3036:
		if (!pll->rate_table)
		init.ops = &rockchip_rk3036_pll_clk_norate_ops;
		else
		init.ops = &rockchip_rk3036_pll_clk_ops;
		break;
		case pll_rk3066:
		if (!pll->rate_table)
		init.ops = &rockchip_rk3066_pll_clk_norate_ops;

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