Commit ea982ba7 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mmc-v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc 

Pull MMC updates from Ulf Hansson:
 "MMC core:
   - Fixup processing of SDIO IRQs during system suspend/resume
   - Add helper function to indicate if SDIO IRQs is enabled

  MMC host:
   - bcm2835: Take SWIOTLB memory size limitation into account
   - dw_mmc: Improve SDIO IRQs support
   - mtk-sd: Various improvements
   - mtk-sd: Improve SDIO IRQs support
   - sdhci-iproc: Add support for emmc2 of the BCM2711
   - sdhci-of-arasan: Add Support for Intel LGM eMMC
   - sdhci-of-aspeed: Add support for the ASPEED SD controller
   - sdhci-of-esdhc: Deal with erratum A011334 support in ls1028a 1.0 SoC
   - sdhci-pci: Prepare to add support of Genesys Logic GL975x
   - sdhci-pci: Add another Id for Intel CML
   - sdhci-pci-o2micro: Fix O2 Host data read/write DLL Lock phase shift issue
   - sunxi: Add support for H5 compatibles"

* tag 'mmc-v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: (59 commits)
  ms_block: fix spelling mistake "randomally" -> "randomly"
  mmc: dw_mmc: hi3798cv200: make array degrees static const, makes object smaller
  mmc: sdhci: Convert to use sdio_irq_claimed()
  mmc: sdhci: Drop redundant code for SDIO IRQs
  mmc: sdhci: Drop redundant check in sdhci_ack_sdio_irq()
  mmc: core: Fixup processing of SDIO IRQs during system suspend/resume
  mmc: core: WARN if SDIO IRQs are enabled for non-powered card in suspend
  mmc: core: Clarify that the ->ack_sdio_irq() callback is mandatory
  mmc: core: Clarify sdio_irq_pending flag for MMC_CAP2_SDIO_IRQ_NOTHREAD
  mmc: core: Move code to get pending SDIO IRQs to a function
  mmc: mtk-sd: Re-store SDIO IRQs mask at system resume
  mmc: dw_mmc: Re-store SDIO IRQs mask at system resume
  mmc: core: Add helper function to indicate if SDIO IRQs is enabled
  mmc: sdhci-pci-o2micro: Fix O2 Host data read/write DLL Lock phase shift issue
  mmc: sdhci-pci-o2micro: Move functions in preparation to fix DLL lock phase shift issue
  mmc: sdhci-pci-o2micro: Change O2 Host PLL and DLL register name
  mmc: sdhci: Fix incorrect switch to HS mode
  mmc: sdhci-of-aspeed: Depend on CONFIG_OF_ADDRESS
  mmc: sdhci-of-aspeed: Allow max-frequency limitation of SDCLK
  mmc: sdhci-of-aspeed: Uphold clocks-on post-condition of set_clock()
  ...
parents 7ad67ca5 b4611979

Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml

+10 −4
Original line number Diff line number Diff line
@@ -30,16 +30,22 @@ properties: 
          - const: allwinner,sun8i-a83t-mmc

          - const: allwinner,sun7i-a20-mmc

      - items:

          - const: allwinner,sun50i-h6-emmc

          - const: allwinner,sun8i-r40-emmc

          - const: allwinner,sun50i-a64-emmc

      - items:

          - const: allwinner,sun50i-h6-mmc

          - const: allwinner,sun8i-r40-mmc

          - const: allwinner,sun50i-a64-mmc

      - items:

          - const: allwinner,sun8i-r40-emmc

          - const: allwinner,sun50i-h5-emmc

          - const: allwinner,sun50i-a64-emmc

      - items:

          - const: allwinner,sun8i-r40-mmc

          - const: allwinner,sun50i-h5-mmc

          - const: allwinner,sun50i-a64-mmc

      - items:

          - const: allwinner,sun50i-h6-emmc

          - const: allwinner,sun50i-a64-emmc

      - items:

          - const: allwinner,sun50i-h6-mmc

          - const: allwinner,sun50i-a64-mmc



  reg:

Documentation/devicetree/bindings/mmc/arasan,sdhci.txt

+17 −0
Original line number Diff line number Diff line
@@ -17,6 +17,8 @@ Required Properties: 
      For this device it is strongly suggested to include arasan,soc-ctl-syscon.

    - "ti,am654-sdhci-5.1", "arasan,sdhci-5.1": TI AM654 MMC PHY

	Note: This binding has been deprecated and moved to [5].

    - "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel LGM eMMC PHY

      For this device it is strongly suggested to include arasan,soc-ctl-syscon.



  [5] Documentation/devicetree/bindings/mmc/sdhci-am654.txt
@@ -80,3 +82,18 @@ Example: 
		phy-names = "phy_arasan";

		#clock-cells = <0>;

	};



	emmc: sdhci@ec700000 {

		compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";

		reg = <0xec700000 0x300>;

		interrupt-parent = <&ioapic1>;

		interrupts = <44 1>;

		clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>,

			 <&cgu0 LGM_GCLK_EMMC>;

		clock-names = "clk_xin", "clk_ahb", "gate";

		clock-output-names = "emmc_cardclock";

		#clock-cells = <0>;

		phys = <&emmc_phy>;

		phy-names = "phy_arasan";

		arasan,soc-ctl-syscon = <&sysconf>;

	};

Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml

0 → 100644
+106 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-or-later

# Copyright 2019 IBM Corp.

%YAML 1.2

---

$id: http://devicetree.org/schemas/mmc/aspeed,sdhci.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: ASPEED SD/SDIO/MMC Controller



maintainers:

  - Andrew Jeffery <andrew@aj.id.au>

  - Ryan Chen <ryanchen.aspeed@gmail.com>



description: |+

  The ASPEED SD/SDIO/eMMC controller exposes two slots implementing the SDIO

  Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit data bus if

  only a single slot is enabled.



  The two slots are supported by a common configuration area. As the SDHCIs for

  the slots are dependent on the common configuration area, they are described

  as child nodes.



properties:

  compatible:

    enum:

      - aspeed,ast2400-sd-controller

      - aspeed,ast2500-sd-controller

      - aspeed,ast2600-sd-controller

  reg:

    maxItems: 1

    description: Common configuration registers

  "#address-cells":

    const: 1

  "#size-cells":

    const: 1

  ranges: true

  clocks:

    maxItems: 1

    description: The SD/SDIO controller clock gate



patternProperties:

  "^sdhci@[0-9a-f]+$":

    type: object

    allOf:

        - $ref: mmc-controller.yaml

    properties:

      compatible:

        enum:

          - aspeed,ast2400-sdhci

          - aspeed,ast2500-sdhci

          - aspeed,ast2600-sdhci

      reg:

        maxItems: 1

        description: The SDHCI registers

      clocks:

        maxItems: 1

        description: The SD bus clock

      interrupts:

        maxItems: 1

        description: The SD interrupt shared between both slots

      sdhci,auto-cmd12:

        type: boolean

        description: Specifies that controller should use auto CMD12

    required:

      - compatible

      - reg

      - clocks

      - interrupts



additionalProperties: false



required:

  - compatible

  - reg

  - "#address-cells"

  - "#size-cells"

  - ranges

  - clocks



examples:

  - |

    #include <dt-bindings/clock/aspeed-clock.h>

    sdc@1e740000 {

            compatible = "aspeed,ast2500-sd-controller";

            reg = <0x1e740000 0x100>;

            #address-cells = <1>;

            #size-cells = <1>;

            ranges = <0 0x1e740000 0x20000>;

            clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;



            sdhci0: sdhci@100 {

                    compatible = "aspeed,ast2500-sdhci";

                    reg = <0x100 0x100>;

                    interrupts = <26>;

                    sdhci,auto-cmd12;

                    clocks = <&syscon ASPEED_CLK_SDIO>;

            };



            sdhci1: sdhci@200 {

                    compatible = "aspeed,ast2500-sdhci";

                    reg = <0x200 0x100>;

                    interrupts = <26>;

                    sdhci,auto-cmd12;

                    clocks = <&syscon ASPEED_CLK_SDIO>;

            };

    };

Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt

+3 −1
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@@ -6,10 +6,12 @@ by mmc.txt and the properties that represent the IPROC SDHCI controller. 
Required properties:

- compatible : Should be one of the following

	       "brcm,bcm2835-sdhci"

	       "brcm,bcm2711-emmc2"

	       "brcm,sdhci-iproc-cygnus"

	       "brcm,sdhci-iproc"



Use brcm2835-sdhci for Rasperry PI.

Use brcm2835-sdhci for the eMMC controller on the BCM2835 (Raspberry Pi) and

bcm2711-emmc2 for the additional eMMC2 controller on BCM2711.



Use sdhci-iproc-cygnus for Broadcom SDHCI Controllers

restricted to 32bit host accesses to SDHCI registers.

MAINTAINERS

+1 −0
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@@ -1462,6 +1462,7 @@ F: arch/arm/mach-artpec 
F:	arch/arm/boot/dts/artpec6*

F:	drivers/clk/axis

F:	drivers/crypto/axis

F:	drivers/mmc/host/usdhi6rol0.c

F:	drivers/pinctrl/pinctrl-artpec*

F:	Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt

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