Commit ea8ca310 authored by Chunyan Zhang's avatar Chunyan Zhang Committed by Stephen Boyd
Browse files

clk: sprd: Add macros for referencing parents without strings 



With the new clk parenting code, clk_init_data was expanded to include
.parent_hws and .parent_data, for clk drivers to specify parents without
name strings of clocks.

Also some macros were added for using these two items to reference
clock parents. Based on that to expand macros for sprd clocks:

- SPRD_*_DATA, take an array of struct clk_parent_data * as its parents
  which should be a combination of .fw_name (devicetree clock-names),
  .hw (pointers to a local struct clk_hw).

- SPRD_*_HW, take a local struct clk_hw pointer, instead of a string, as
  its parent.

- SPRD_*_FW_NAME, take a string of clock-names decleared in the device
  tree as the clock parent.

Signed-off-by: default avatarChunyan Zhang <chunyan.zhang@unisoc.com>
Link: https://lkml.kernel.org/r/20200304072730.9193-6-zhang.lyra@gmail.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent be7ef655

drivers/clk/sprd/composite.h

+28 −11
Original line number Diff line number Diff line
@@ -18,26 +18,43 @@ struct sprd_comp { 
	struct sprd_clk_common	common;

};



#define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table,	\

			_mshift, _mwidth, _dshift, _dwidth, _flags)	\

#define SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table,	\

				 _mshift, _mwidth, _dshift, _dwidth,	\

				 _flags, _fn)				\

	struct sprd_comp _struct = {					\

		.mux	= _SPRD_MUX_CLK(_mshift, _mwidth, _table),	\

		.div	= _SPRD_DIV_CLK(_dshift, _dwidth),		\

		.common = {						\

			.regmap		= NULL,				\

			.reg		= _reg,				\

			.hw.init = CLK_HW_INIT_PARENTS(_name,		\

						       _parent,		\

						       &sprd_comp_ops,	\

						       _flags),		\

			.hw.init = _fn(_name, _parent,			\

				       &sprd_comp_ops, _flags),		\

			 }						\

	}



#define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table,	\

			    _mshift, _mwidth, _dshift, _dwidth, _flags)	\

	SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table,	\

				 _mshift, _mwidth, _dshift, _dwidth,	\

				 _flags, CLK_HW_INIT_PARENTS)



#define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift,		\

		      _mwidth, _dshift, _dwidth, _flags)		\

	SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg,	\

			    NULL, _mshift, _mwidth,		\

			    _dshift, _dwidth, _flags)

	SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, NULL,	\

			    _mshift, _mwidth, _dshift, _dwidth, _flags)



#define SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, _table,	\

				 _mshift, _mwidth, _dshift,		\

				 _dwidth, _flags)			\

	SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table,	\

				 _mshift, _mwidth, _dshift, _dwidth,	\

				 _flags, CLK_HW_INIT_PARENTS_DATA)



#define SPRD_COMP_CLK_DATA(_struct, _name, _parent, _reg, _mshift,	\

			   _mwidth, _dshift, _dwidth, _flags)		\

	SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg,	NULL,	\

				 _mshift, _mwidth, _dshift, _dwidth,	\

				 _flags)



static inline struct sprd_comp *hw_to_sprd_comp(const struct clk_hw *hw)

{

drivers/clk/sprd/div.h

+14 −6
Original line number Diff line number Diff line
@@ -35,20 +35,28 @@ struct sprd_div { 
	struct sprd_clk_common	common;

};



#define SPRD_DIV_CLK(_struct, _name, _parent, _reg,			\

			_shift, _width, _flags)				\

#define SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg,		\

				_shift, _width, _flags, _fn)		\

	struct sprd_div _struct = {					\

		.div	= _SPRD_DIV_CLK(_shift, _width),		\

		.common	= {						\

			.regmap		= NULL,				\

			.reg		= _reg,				\

			.hw.init	= CLK_HW_INIT(_name,		\

						      _parent,		\

						      &sprd_div_ops,	\

						      _flags),		\

			.hw.init	= _fn(_name, _parent,		\

					      &sprd_div_ops, _flags),	\

		}							\

	}



#define SPRD_DIV_CLK(_struct, _name, _parent, _reg,			\

		     _shift, _width, _flags)				\

	SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg,		\

				_shift, _width, _flags, CLK_HW_INIT)



#define SPRD_DIV_CLK_HW(_struct, _name, _parent, _reg,			\

			_shift, _width, _flags)				\

	SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg,		\

				_shift, _width, _flags, CLK_HW_INIT_HW)



static inline struct sprd_div *hw_to_sprd_div(const struct clk_hw *hw)

{

	struct sprd_clk_common *common = hw_to_sprd_clk_common(hw);

drivers/clk/sprd/gate.h

+96 −13
Original line number Diff line number Diff line
@@ -19,9 +19,9 @@ struct sprd_gate { 
	struct sprd_clk_common	common;

};



#define SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg,	\

#define SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg,	\

				    _sc_offset, _enable_mask, _flags,	\

				    _gate_flags, _udelay, _ops)		\

				    _gate_flags, _udelay, _ops, _fn)	\

	struct sprd_gate _struct = {					\

		.enable_mask	= _enable_mask,				\

		.sc_offset	= _sc_offset,				\
@@ -30,35 +30,118 @@ struct sprd_gate { 
		.common	= {						\

			.regmap		= NULL,				\

			.reg		= _reg,				\

			.hw.init	= CLK_HW_INIT(_name,		\

						      _parent,		\

						      _ops,		\

						      _flags),		\

			.hw.init	= _fn(_name, _parent,		\

					      _ops, _flags),		\

		}							\

	}



#define SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg,	\

				    _sc_offset, _enable_mask, _flags,	\

				    _gate_flags, _udelay, _ops)		\

	SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg,	\

				    _sc_offset, _enable_mask, _flags,	\

				    _gate_flags, _udelay, _ops, CLK_HW_INIT)



#define SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset,	\

			     _enable_mask, _flags, _gate_flags, _ops)	\

	SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg,	\

				    _sc_offset, _enable_mask, _flags,	\

				    _gate_flags, 0, _ops)



#define SPRD_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset,	\

			 _enable_mask, _flags, _gate_flags)		\

	SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset,	\

			     _enable_mask, _flags, _gate_flags,		\

			     &sprd_sc_gate_ops)



#define SPRD_GATE_CLK(_struct, _name, _parent, _reg,			\

		      _enable_mask, _flags, _gate_flags)		\

	SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, 0,		\

			     _enable_mask, _flags, _gate_flags,		\

			     &sprd_gate_ops)



#define SPRD_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset,	\

#define SPRD_PLL_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset,	\

			     _enable_mask, _flags, _gate_flags,		\

			     _udelay)					\

	SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg,	\

				    _sc_offset,	_enable_mask, _flags,	\

				    _gate_flags, _udelay,		\

				    &sprd_pll_sc_gate_ops)





#define SPRD_SC_GATE_CLK_HW_OPS_UDELAY(_struct, _name, _parent, _reg,	\

				       _sc_offset, _enable_mask,	\

				       _flags, _gate_flags,		\

				       _udelay, _ops)			\

	SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg,	\

				    _sc_offset, _enable_mask, _flags,	\

				    _gate_flags, _udelay, _ops,		\

				    CLK_HW_INIT_HW)



#define SPRD_SC_GATE_CLK_HW_OPS(_struct, _name, _parent, _reg,		\

				_sc_offset, _enable_mask, _flags,	\

				_gate_flags, _ops)			\

	SPRD_SC_GATE_CLK_HW_OPS_UDELAY(_struct, _name, _parent, _reg,	\

				       _sc_offset, _enable_mask,	\

				       _flags, _gate_flags, 0, _ops)



#define SPRD_SC_GATE_CLK_HW(_struct, _name, _parent, _reg,		\

			    _sc_offset, _enable_mask, _flags,		\

			    _gate_flags)				\

	SPRD_SC_GATE_CLK_HW_OPS(_struct, _name, _parent, _reg,		\

				_sc_offset, _enable_mask, _flags,	\

				_gate_flags, &sprd_sc_gate_ops)



#define SPRD_GATE_CLK_HW(_struct, _name, _parent, _reg,			\

			 _enable_mask, _flags, _gate_flags)		\

	SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset,	\

	SPRD_SC_GATE_CLK_HW_OPS(_struct, _name, _parent, _reg, 0,	\

				_enable_mask, _flags, _gate_flags,	\

			     &sprd_sc_gate_ops)

				&sprd_gate_ops)



#define SPRD_PLL_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset,	\

			    _enable_mask, _flags, _gate_flags, _udelay)	\

	SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg,	\

#define SPRD_PLL_SC_GATE_CLK_HW(_struct, _name, _parent, _reg,		\

				_sc_offset, _enable_mask, _flags,	\

				_gate_flags, _udelay)			\

	SPRD_SC_GATE_CLK_HW_OPS_UDELAY(_struct, _name, _parent, _reg,	\

				       _sc_offset, _enable_mask,	\

				       _flags, _gate_flags, _udelay,	\

				       &sprd_pll_sc_gate_ops)



#define SPRD_SC_GATE_CLK_FW_NAME_OPS_UDELAY(_struct, _name, _parent,	\

					    _reg, _sc_offset,		\

					    _enable_mask, _flags,	\

					    _gate_flags, _udelay, _ops)	\

	SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg,	\

				    _sc_offset, _enable_mask, _flags,	\

				    _gate_flags, _udelay, _ops,		\

				    CLK_HW_INIT_FW_NAME)



#define SPRD_SC_GATE_CLK_FW_NAME_OPS(_struct, _name, _parent, _reg,	\

				     _sc_offset, _enable_mask, _flags,	\

				     _gate_flags, _ops)			\

	SPRD_SC_GATE_CLK_FW_NAME_OPS_UDELAY(_struct, _name, _parent,	\

					    _reg, _sc_offset,		\

					    _enable_mask, _flags,	\

					    _gate_flags, 0, _ops)



#define SPRD_SC_GATE_CLK_FW_NAME(_struct, _name, _parent, _reg,		\

				 _sc_offset, _enable_mask, _flags,	\

				 _gate_flags)				\

	SPRD_SC_GATE_CLK_FW_NAME_OPS(_struct, _name, _parent, _reg,	\

				     _sc_offset, _enable_mask, _flags,	\

				     _gate_flags, &sprd_sc_gate_ops)



#define SPRD_GATE_CLK_FW_NAME(_struct, _name, _parent, _reg,		\

			      _enable_mask, _flags, _gate_flags)	\

	SPRD_SC_GATE_CLK_FW_NAME_OPS(_struct, _name, _parent, _reg, 0,	\

				     _enable_mask, _flags, _gate_flags,	\

				     &sprd_gate_ops)



#define SPRD_PLL_SC_GATE_CLK_FW_NAME(_struct, _name, _parent, _reg,	\

				     _sc_offset, _enable_mask, _flags,	\

				     _gate_flags, _udelay)		\

	SPRD_SC_GATE_CLK_FW_NAME_OPS_UDELAY(_struct, _name, _parent,	\

					    _reg, _sc_offset,		\

					    _enable_mask, _flags,	\

					    _gate_flags, _udelay,	\

					    &sprd_pll_sc_gate_ops)

drivers/clk/sprd/mux.h

+21 −7
Original line number Diff line number Diff line
@@ -36,26 +36,40 @@ struct sprd_mux { 
		.table	= _table,			\

	}



#define SPRD_MUX_CLK_TABLE(_struct, _name, _parents, _table,		\

				     _reg, _shift, _width,		\

				     _flags)				\

#define SPRD_MUX_CLK_HW_INIT_FN(_struct, _name, _parents, _table,	\

				_reg, _shift, _width, _flags, _fn)	\

	struct sprd_mux _struct = {					\

		.mux	= _SPRD_MUX_CLK(_shift, _width, _table),	\

		.common	= {						\

			.regmap		= NULL,				\

			.reg		= _reg,				\

			.hw.init = CLK_HW_INIT_PARENTS(_name,		\

						       _parents,	\

						       &sprd_mux_ops,	\

						       _flags),		\

			.hw.init = _fn(_name, _parents,			\

				       &sprd_mux_ops, _flags),		\

		}							\

	}



#define SPRD_MUX_CLK_TABLE(_struct, _name, _parents, _table,		\

			   _reg, _shift, _width, _flags)		\

	SPRD_MUX_CLK_HW_INIT_FN(_struct, _name, _parents, _table,	\

				_reg, _shift, _width, _flags,		\

				CLK_HW_INIT_PARENTS)



#define SPRD_MUX_CLK(_struct, _name, _parents, _reg,		\

		     _shift, _width, _flags)			\

	SPRD_MUX_CLK_TABLE(_struct, _name, _parents, NULL,	\

			   _reg, _shift, _width, _flags)



#define SPRD_MUX_CLK_DATA_TABLE(_struct, _name, _parents, _table,	\

				_reg, _shift, _width, _flags)		\

	SPRD_MUX_CLK_HW_INIT_FN(_struct, _name, _parents, _table,	\

				_reg, _shift, _width, _flags,		\

				CLK_HW_INIT_PARENTS_DATA)



#define SPRD_MUX_CLK_DATA(_struct, _name, _parents, _reg,		\

			  _shift, _width, _flags)			\

	SPRD_MUX_CLK_DATA_TABLE(_struct, _name, _parents, NULL,		\

				_reg, _shift, _width, _flags)



static inline struct sprd_mux *hw_to_sprd_mux(const struct clk_hw *hw)

{

	struct sprd_clk_common *common = hw_to_sprd_clk_common(hw);

drivers/clk/sprd/pll.h

+37 −18
Original line number Diff line number Diff line
@@ -61,9 +61,10 @@ struct sprd_pll { 
	struct sprd_clk_common	common;

};



#define SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg,	\

#define SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg,	\

			    _regs_num, _itable, _factors,	\

				    _udelay, _k1, _k2, _fflag, _fvco)	\

			    _udelay, _k1, _k2, _fflag,		\

			    _fvco, _fn)				\

	struct sprd_pll _struct = {				\

		.regs_num	= _regs_num,			\

		.itable		= _itable,			\
@@ -76,13 +77,18 @@ struct sprd_pll { 
		.common		= {				\

			.regmap		= NULL,			\

			.reg		= _reg,			\

			.hw.init	= CLK_HW_INIT(_name,		\

						      _parent,		\

						      &sprd_pll_ops,	\

						      0),		\

			.hw.init	= _fn(_name, _parent,	\

					      &sprd_pll_ops, 0),\

		},						\

	}



#define SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg,	\

				    _regs_num, _itable, _factors,	\

				    _udelay, _k1, _k2, _fflag, _fvco)	\

	SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num,	\

			    _itable, _factors, _udelay, _k1, _k2,	\

			    _fflag, _fvco, CLK_HW_INIT)



#define SPRD_PLL_WITH_ITABLE_K(_struct, _name, _parent, _reg,		\

			       _regs_num, _itable, _factors,		\

			       _udelay, _k1, _k2)			\
@@ -96,6 +102,19 @@ struct sprd_pll { 
				    _regs_num, _itable, _factors,	\

				    _udelay, 1000, 1000, 0, 0)



#define SPRD_PLL_FW_NAME(_struct, _name, _parent, _reg, _regs_num,	\

			 _itable, _factors, _udelay, _k1, _k2,		\

			 _fflag, _fvco)					\

	SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num,	\

			    _itable, _factors, _udelay, _k1, _k2,	\

			    _fflag, _fvco, CLK_HW_INIT_FW_NAME)



#define SPRD_PLL_HW(_struct, _name, _parent, _reg, _regs_num, _itable,	\

		    _factors, _udelay, _k1, _k2, _fflag, _fvco)		\

	SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num,	\

			    _itable, _factors, _udelay, _k1, _k2,	\

			    _fflag, _fvco, CLK_HW_INIT_HW)



static inline struct sprd_pll *hw_to_sprd_pll(struct clk_hw *hw)

{

	struct sprd_clk_common *common = hw_to_sprd_clk_common(hw);

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