Commit ea84c842 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'net-ethernet-ti-k3-introduce-common-platform-time-sync-driver-cpts' 

Grygorii Strashko says:

====================
net: ethernet: ti: k3: introduce common platform time sync driver - cpts

This series introduced support for significantly upgraded TI A65x/J721E Common
platform time sync (CPTS) modules which are part of AM65xx Time Synchronization
Architecture [1].
The TI A65x/J721E now contain more than one CPTS instance:
- MCU CPSW CPTS (IEEE 1588 compliant)
- Main NAVSS CPTS (central)
- PCIe CPTS(s) (PTM  compliant)
- J721E: Main CPSW9g CPTS (IEEE 1588 compliant)
which can work as separately as interact to each other through Time Sync Router
(TSR) and Compare Event Router (CER). In addition there are also ICSS-G IEP
blocks which can perform similar timsync functions, but require FW support.
More info also available in TRM [2][3]. Not all above modules are available
to the Linux by as of now as some of them are reserved for RTOS/FW purposes.

The scope of this submission is TI A65x/J721E CPSW CPTS and Main NAVSS CPTS,
and TSR was used for testing purposes.
                                                                       +---------------------------+
                                                                       | MCU CPSW                  |
+-------------------+           +------------------------+             |                TS         |
| Main Navss CPTS   |           | Time Sync Router (TSR) |             |          +-------------+  |
|                   |           |                        |             |          |             |  |
|            HW1_TS +<----------+                        |             | +--------v-----+    +--+--+
|                   |           |                        |             | |        CPTS  |    |Port |
|              ...  |           |                        |           X+-->HW1_TS        |    |     |
|            HW8_TS <------------<---------+             |           X|-->HW2_TS        |    +--^--+
|                   |           |          |             +--------------->HW3_TS        |       |  |
|                   |           |          |             +--------------->HW4_TS        |       |  |
|                   |           |          |             |             | |              |       |  |
|                   |           |          |             |             | |              |       |  |
|            Genf0  +----------->          (A)---------+ +<--------------+Genf0         |       |  |
|                   |           |          |             |             | |              |       |  |
|              ...  |           |          +-----------> <---------------+Genf1     ESTf+-------+  |
|                   |           |                        |             | |              |          |
|                   |           |                        |             | +--------------+          |
|            Genf8  +---------->+                        |             |                           |
|                   |           |    SYNC0 ...    SYNC3  |             |                           |
+-------------------+           +------+------------+----+             +---------------------------+
                                       +            +
                                       X            X
(A) shows possible routing path for MCU CPSW CPTS Genf0 signal as an example.

Main features of the new TI A65x/J721E CPTS modules are:
- 64-bit timestamp/counter mode support in ns by using add_val
- implemented in HW PPM and nudge adjustment.
- control of time sync events via interrupt or polling
- selection of multiple external reference clock sources
- hardware timestamp of ext. inputs events (HWx_TS_PUSH)
- periodic generator function outputs (TS_GENFx)
- (CPSW only) Ethernet Enhanced Scheduled Traffic Operations (CPTS_ESTFn),
  which drives TSN schedule
- timestamping of all RX packets bypassing CPTS FIFO

Patch 1 - DT bindings
Patch 2 - the AM65x/J721E driver
Patch 3 - enables packet timestamping support in TI AM65x/J721E MCU CPSW driver.
Patches 4-7 - DT updates.

=== PTP Testing:

phc2sys -s CLOCK_REALTIME -c eth0 -m -O 0 -u30
phc2sys[627.331]: eth0 rms 409912446712787392 max 1587584079521858304 freq  -6665 +/- 35040 delay   832 +/-  27
phc2sys[657.335]: eth0 rms   33 max   66 freq     -0 +/-  28 delay   820 +/-  30
phc2sys[687.339]: eth0 rms   37 max   70 freq     -1 +/-  32 delay   830 +/-  29
phc2sys[717.343]: eth0 rms   33 max   71 freq     -0 +/-  29 delay   828 +/-  23
phc2sys[747.346]: eth0 rms   35 max   75 freq     -0 +/-  31 delay   829 +/-  26
phc2sys[777.350]: eth0 rms   37 max   68 freq     -1 +/-  32 delay   825 +/-  25
phc2sys[807.354]: eth0 rms   28 max   57 freq     -1 +/-  25 delay   824 +/-  21
phc2sys[837.358]: eth0 rms   43 max   81 freq     -1 +/-  37 delay   836 +/-  23
phc2sys[867.361]: eth0 rms   33 max   74 freq     +0 +/-  29 delay   828 +/-  24
phc2sys[897.365]: eth0 rms   35 max   77 freq     -2 +/-  30 delay   824 +/-  25
phc2sys[927.369]: eth0 rms   28 max   50 freq     +0 +/-  25 delay   825 +/-  25

ptp4l -P -2 -H -i eth0 -l 6 -m -q -p /dev/ptp1 -f ptp.cfg -s
ptp4l[22095.754]: port 1: MASTER to UNCALIBRATED on RS_SLAVE
ptp4l[22097.754]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED
ptp4l[22159.757]: rms  317 max 1418 freq    +79 +/- 186 delay   410 +/-   1
ptp4l[22223.760]: rms    9 max   24 freq    +42 +/-  12 delay   409 +/-   1
ptp4l[22287.763]: rms   10 max   28 freq    +41 +/-  11 delay   410 +/-   1
ptp4l[22351.767]: rms   10 max   26 freq    +34 +/-  12 delay   410 +/-   1
ptp4l[22415.770]: rms   10 max   26 freq    +49 +/-  14 delay   410 +/-   1

=== Ext. HW_TS and Genf testing:

For testing purposes Time Sync Router (TSR) can be modeled in DT as pin controller
+       timesync_router: timesync_router@A40000 {
+               compatible = "pinctrl-single";
+               reg = <0x0 0xA40000 0x0 0x800>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               #pinctrl-cells = <1>;
+               pinctrl-single,register-width = <32>;
+               pinctrl-single,function-mask = <0x800007ff>;
+       };

then signals routing can be done in board file, for example:
+#define TS_OFFSET(pa, val)     (0x4+(pa)*4) (0x80000000 | val)
+
+&timesync_router {
+       pinctrl-names = "default";
+       pinctrl-0 = <&mcu_cpts>;
+
+       /* Example of the timesync routing */
+       mcu_cpts: mcu_cpts {
+               pinctrl-single,pins = <
+                       /* [cpts genf1] in13 -> out25 [cpts hw4_push] */
+                       TS_OFFSET(25, 13)
+                       /* [cpts genf1] in13 -> out0 [main cpts hw1_push] */
+                       TS_OFFSET(0, 13)
+                       /* [main cpts genf0] in4 -> out1 [main cpts hw2_push] */
+                       TS_OFFSET(1, 4)
+                       /* [main cpts genf0] in4 -> out24 [cpts hw3_push] */
+                       TS_OFFSET(24, 4)
+               >;
+       };
+};

will create link:
    cpsw cpts Genf1 -> main cpts hw1_push
                    -> cpsw cpts hw4_push

    main cpts Genf0 -> main cpts hw2_push
                    -> cpsw cpts hw3_push

 testptp -d /dev/ptp0 -i 0 -p 1000000000
 periodic output request okay
 testptp -d /dev/ptp0 -i 1 -e 5
 external time stamp request okay
 event index 1 at 22583.000000025
 event index 1 at 22584.000000025
 event index 1 at 22585.000000025
 event index 1 at 22586.000000025
 event index 1 at 22587.000000025
 testptp -d /dev/ptp1 -i 2 -e 5
 external time stamp request okay
 event index 2 at 1587606764.249304554
 event index 2 at 1587606765.249304467
 event index 2 at 1587606766.249304380
 event index 2 at 1587606767.249304293
 event index 2 at 1587606768.249304206

[1] https://www.ti.com/lit/pdf/spracp7
[2] https://www.ti.com/lit/pdf/sprz452
[3] https://www.ti.com/lit/pdf/spruil1


====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 1248dc00 461d6d05

Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml

+7 −0
Original line number Diff line number Diff line
@@ -144,6 +144,13 @@ patternProperties: 
    description:

      CPSW MDIO bus.



  "^cpts$":

    type: object

    allOf:

      - $ref: "ti,am654-cpts.yaml#"

    description:

      CPSW Common Platform Time Sync (CPTS) module.



required:

  - compatible

  - reg

Documentation/devicetree/bindings/net/ti,k3-am654-cpts.yaml

0 → 100644
+152 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/net/ti,am654-cpts.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: The TI AM654x/J721E Common Platform Time Sync (CPTS) module Device Tree Bindings



maintainers:

  - Grygorii Strashko <grygorii.strashko@ti.com>

  - Sekhar Nori <nsekhar@ti.com>



description: |+

  The TI AM654x/J721E CPTS module is used to facilitate host control of time

  sync operations.

  Main features of CPTS module are

  - selection of multiple external clock sources

  - Software control of time sync events via interrupt or polling

  - 64-bit timestamp mode in ns with PPM and nudge adjustment.

  - hardware timestamp push inputs (HWx_TS_PUSH)

  - timestamp counter compare output (TS_COMP)

  - timestamp counter bit output (TS_SYNC)

  - periodic Generator function outputs (TS_GENFx)

  - Ethernet Enhanced Scheduled Traffic Operations (CPTS_ESTFn) (TSN)

  - external hardware timestamp push inputs (HWx_TS_PUSH) timestamping



   Depending on integration it enables compliance with the IEEE 1588-2008

   standard for a precision clock synchronization protocol, Ethernet Enhanced

   Scheduled Traffic Operations (CPTS_ESTFn) and PCIe Subsystem Precision Time

   Measurement (PTM).



  TI AM654x/J721E SoCs has several similar CPTS modules integrated into the

  different parts of the system which could be synchronized with each other

  - Main CPTS

  - MCU CPSW CPTS with IEEE 1588-2008 support

  - PCIe subsystem CPTS for PTM support



  Depending on CPTS module integration and when CPTS is integral part of

  another module (MCU CPSW for example) "compatible" and "reg" can

  be omitted - parent module is fully responsible for CPTS enabling and

  configuration.



properties:

  $nodename:

    pattern: "^cpts(@.*|-[0-9a-f])*$"



  compatible:

    oneOf:

      - const: ti,am65-cpts

      - const: ti,j721e-cpts



  reg:

    maxItems: 1

    description:

       The physical base address and size of CPTS IO range



  reg-names:

    items:

      - const: cpts



  clocks:

    description: CPTS reference clock



  clock-names:

    items:

      - const: cpts



  interrupts-extended:

    items:

      - description: CPTS events interrupt



  interrupt-names:

    items:

      - const: "cpts"



  ti,cpts-ext-ts-inputs:

    allOf:

      - $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 8

    description:

        Number of hardware timestamp push inputs (HWx_TS_PUSH)



  ti,cpts-periodic-outputs:

    allOf:

      - $ref: /schemas/types.yaml#/definitions/uint32

    maximum: 8

    description:

         Number of timestamp Generator function outputs (TS_GENFx)



  refclk-mux:

    type: object

    description: CPTS reference clock multiplexer clock

    properties:

      '#clock-cells':

        const: 0



      clocks:

        maxItems: 8



      assigned-clocks:

        maxItems: 1



      assigned-clocks-parents:

        maxItems: 1



    required:

      - clocks



required:

  - clocks

  - clock-names

  - interrupts-extended

  - interrupt-names



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    cpts@310d0000 {

         compatible = "ti,am65-cpts";

         reg = <0x0 0x310d0000 0x0 0x400>;

         reg-names = "cpts";

         clocks = <&main_cpts_mux>;

         clock-names = "cpts";

         interrupts-extended = <&k3_irq 163 0 IRQ_TYPE_LEVEL_HIGH>;

         interrupt-names = "cpts";

         ti,cpts-periodic-outputs = <6>;

         ti,cpts-ext-ts-inputs = <8>;



         main_cpts_mux: refclk-mux {

               #clock-cells = <0>;

               clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,

                        <&k3_clks 157 91>, <&k3_clks 157 77>,

                        <&k3_clks 157 102>, <&k3_clks 157 80>,

                        <&k3_clks 120 3>, <&k3_clks 121 3>;

               assigned-clocks = <&main_cpts_mux>;

               assigned-clock-parents = <&k3_clks 118 11>;

         };

    };

  - |



    cpts {

             clocks = <&k3_clks 18 2>;

             clock-names = "cpts";

             interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;

             interrupt-names = "cpts";

             ti,cpts-ext-ts-inputs = <4>;

             ti,cpts-periodic-outputs = <2>;

    };

arch/arm64/boot/dts/ti/k3-am65-main.dtsi

+22 −0
Original line number Diff line number Diff line
@@ -570,6 +570,28 @@ 
						<0x5>; /* RX_CHAN */

			ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */

		};



		cpts@310d0000 {

			compatible = "ti,am65-cpts";

			reg = <0x0 0x310d0000 0x0 0x400>;

			reg-names = "cpts";

			clocks = <&main_cpts_mux>;

			clock-names = "cpts";

			interrupts-extended = <&intr_main_navss 163 0>;

			interrupt-names = "cpts";

			ti,cpts-periodic-outputs = <6>;

			ti,cpts-ext-ts-inputs = <8>;



			main_cpts_mux: refclk-mux {

				#clock-cells = <0>;

				clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,

					<&k3_clks 118 6>, <&k3_clks 118 3>,

					<&k3_clks 118 8>, <&k3_clks 118 14>,

					<&k3_clks 120 3>, <&k3_clks 121 3>;

				assigned-clocks = <&main_cpts_mux>;

				assigned-clock-parents = <&k3_clks 118 5>;

			};

		};

	};



	main_gpio0:  main_gpio0@600000 {

arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi

+19 −0
Original line number Diff line number Diff line
@@ -247,5 +247,24 @@ 
			clock-names = "fck";

			bus_freq = <1000000>;

		};



		cpts {

			clocks = <&mcu_cpsw_cpts_mux>;

			clock-names = "cpts";

			interrupts-extended = <&gic500 GIC_SPI 570 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "cpts";

			ti,cpts-ext-ts-inputs = <4>;

			ti,cpts-periodic-outputs = <2>;



			mcu_cpsw_cpts_mux: refclk-mux {

				#clock-cells = <0>;

				clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,

					<&k3_clks 118 6>, <&k3_clks 118 3>,

					<&k3_clks 118 8>, <&k3_clks 118 14>,

					<&k3_clks 120 3>, <&k3_clks 121 3>;

				assigned-clocks = <&mcu_cpsw_cpts_mux>;

				assigned-clock-parents = <&k3_clks 118 5>;

			};

		};

	};

};

arch/arm64/boot/dts/ti/k3-j721e-main.dtsi

+12 −0
Original line number Diff line number Diff line
@@ -254,6 +254,18 @@ 
						<0x0c>; /* RX_UHCHAN */

			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */

		};



		cpts@310d0000 {

			compatible = "ti,j721e-cpts";

			reg = <0x0 0x310d0000 0x0 0x400>;

			reg-names = "cpts";

			clocks = <&k3_clks 201 1>;

			clock-names = "cpts";

			interrupts-extended = <&main_navss_intr 201 0>;

			interrupt-names = "cpts";

			ti,cpts-periodic-outputs = <6>;

			ti,cpts-ext-ts-inputs = <8>;

		};

	};



	main_pmx0: pinmux@11c000 {

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