Commit ea5311c7 authored by Alex Williamson's avatar Alex Williamson Committed by Bjorn Helgaas
Browse files

PCI: Fix PCIe capability sizes 



PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 defines the size of the PCIe capability
structure for v1 devices with link, but we also have a need in the vfio
code for sizing the capability for devices without link, such as Root
Complex Integrated Endpoints.  Create a separate define for this ending the
structure before the link fields.

Additionally, this reveals that PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 is currently
incorrect, ending the capability length before the v2 link fields.  Rename
this to specify an RC Integrated Endpoint (no link) capability length and
move PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 to include the link fields as we have
for the v1 version.

Signed-off-by: default avatarAlex Williamson <alex.williamson@redhat.com>
[bhelgaas: add "_" in "PCI_CAP_EXP_RC ENDPOINT_SIZEOF_V2 44"]
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarEric Auger <eric.auger@redhat.com>
parent b63773a8

include/uapi/linux/pci_regs.h

+4 −2
Original line number Diff line number Diff line
@@ -513,6 +513,7 @@ 
#define  PCI_EXP_DEVSTA_URD	0x0008	/* Unsupported Request Detected */

#define  PCI_EXP_DEVSTA_AUXPD	0x0010	/* AUX Power Detected */

#define  PCI_EXP_DEVSTA_TRPND	0x0020	/* Transactions Pending */

#define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V1	12	/* v1 endpoints without link end here */

#define PCI_EXP_LNKCAP		12	/* Link Capabilities */

#define  PCI_EXP_LNKCAP_SLS	0x0000000f /* Supported Link Speeds */

#define  PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */
@@ -556,7 +557,7 @@ 
#define  PCI_EXP_LNKSTA_DLLLA	0x2000	/* Data Link Layer Link Active */

#define  PCI_EXP_LNKSTA_LBMS	0x4000	/* Link Bandwidth Management Status */

#define  PCI_EXP_LNKSTA_LABS	0x8000	/* Link Autonomous Bandwidth Status */

#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1	20	/* v1 endpoints end here */

#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1	20	/* v1 endpoints with link end here */

#define PCI_EXP_SLTCAP		20	/* Slot Capabilities */

#define  PCI_EXP_SLTCAP_ABP	0x00000001 /* Attention Button Present */

#define  PCI_EXP_SLTCAP_PCP	0x00000002 /* Power Controller Present */
@@ -639,7 +640,7 @@ 
#define  PCI_EXP_DEVCTL2_OBFF_MSGB_EN	0x4000	/* Enable OBFF Message type B */

#define  PCI_EXP_DEVCTL2_OBFF_WAKE_EN	0x6000	/* OBFF using WAKE# signaling */

#define PCI_EXP_DEVSTA2		42	/* Device Status 2 */

#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2	44	/* v2 endpoints end here */

#define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2	44	/* v2 endpoints without link end here */

#define PCI_EXP_LNKCAP2		44	/* Link Capabilities 2 */

#define  PCI_EXP_LNKCAP2_SLS_2_5GB	0x00000002 /* Supported Speed 2.5GT/s */

#define  PCI_EXP_LNKCAP2_SLS_5_0GB	0x00000004 /* Supported Speed 5.0GT/s */
@@ -647,6 +648,7 @@ 
#define  PCI_EXP_LNKCAP2_CROSSLINK	0x00000100 /* Crosslink supported */

#define PCI_EXP_LNKCTL2		48	/* Link Control 2 */

#define PCI_EXP_LNKSTA2		50	/* Link Status 2 */

#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2	52	/* v2 endpoints with link end here */

#define PCI_EXP_SLTCAP2		52	/* Slot Capabilities 2 */

#define PCI_EXP_SLTCTL2		56	/* Slot Control 2 */

#define PCI_EXP_SLTSTA2		58	/* Slot Status 2 */

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