Commit ea530388 authored by Kuogee Hsieh's avatar Kuogee Hsieh Committed by Rob Clark
Browse files

drm/msm/dp: skip checking LINK_STATUS_UPDATED bit 



Some dongle will not clear LINK_STATUS_UPDATED bit after
DPCD read which cause link training failed. This patch
just read 6 bytes of DPCD link status from sink and return
without checking LINK_STATUS_UPDATED bit.
Only 8 bits are used to represent link rate at sinker DPCD.
The really link rate is 2.7Mb times the 8 bits value.
For example, 0x0A at DPCD is equal to 2.7Gb (10 * 2.7Mb).
This patch also convert 8 bits value of DPCD to really link
rate to fix worng link rate error during phy compliance test.

Fixes: 6625e263 ("drm/msm/dp: DisplayPort PHY compliance tests fixup")
Signed-off-by: default avatarKuogee Hsieh <khsieh@codeaurora.org>
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 231a04fc

drivers/gpu/drm/msm/dp/dp_ctrl.c

+6 −14
Original line number Diff line number Diff line
@@ -1064,23 +1064,15 @@ static bool dp_ctrl_train_pattern_set(struct dp_ctrl_private *ctrl, 
static int dp_ctrl_read_link_status(struct dp_ctrl_private *ctrl,

				    u8 *link_status)

{

	int len = 0;

	u32 const offset = DP_LANE_ALIGN_STATUS_UPDATED - DP_LANE0_1_STATUS;

	u32 link_status_read_max_retries = 100;

	int ret = 0, len;



	while (--link_status_read_max_retries) {

		len = drm_dp_dpcd_read_link_status(ctrl->aux,

			link_status);

	len = drm_dp_dpcd_read_link_status(ctrl->aux, link_status);

	if (len != DP_LINK_STATUS_SIZE) {

		DRM_ERROR("DP link status read failed, err: %d\n", len);

			return len;

		}



		if (!(link_status[offset] & DP_LINK_STATUS_UPDATED))

			return 0;

		ret = -EINVAL;

	}



	return -ETIMEDOUT;

	return ret;

}



static int dp_ctrl_link_train_1(struct dp_ctrl_private *ctrl,

drivers/gpu/drm/msm/dp/dp_link.c

+14 −15
Original line number Diff line number Diff line
@@ -773,7 +773,8 @@ static int dp_link_process_link_training_request(struct dp_link_private *link) 
			link->request.test_lane_count);



	link->dp_link.link_params.num_lanes = link->request.test_lane_count;

	link->dp_link.link_params.rate = link->request.test_link_rate;

	link->dp_link.link_params.rate = 

		drm_dp_bw_code_to_link_rate(link->request.test_link_rate);



	return 0;

}
@@ -943,20 +944,18 @@ static u8 get_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r) 
 */

static int dp_link_process_link_status_update(struct dp_link_private *link)

{

	if (!(get_link_status(link->link_status,

				DP_LANE_ALIGN_STATUS_UPDATED) &

				DP_LINK_STATUS_UPDATED) ||

			(drm_dp_clock_recovery_ok(link->link_status,

					link->dp_link.link_params.num_lanes) &&

			drm_dp_channel_eq_ok(link->link_status,

					link->dp_link.link_params.num_lanes)))

		return -EINVAL;

       bool channel_eq_done = drm_dp_channel_eq_ok(link->link_status,

                       link->dp_link.link_params.num_lanes);



       bool clock_recovery_done = drm_dp_clock_recovery_ok(link->link_status,

                       link->dp_link.link_params.num_lanes);



       DRM_DEBUG_DP("channel_eq_done = %d, clock_recovery_done = %d\n",

			drm_dp_clock_recovery_ok(link->link_status,

			link->dp_link.link_params.num_lanes),

			drm_dp_clock_recovery_ok(link->link_status,

			link->dp_link.link_params.num_lanes));

                        channel_eq_done, clock_recovery_done);



       if (channel_eq_done && clock_recovery_done)

               return -EINVAL;





       return 0;

}

CRA Git | Maintained and supported by SUSTech CRA and CCSE