Commit e9bcc1e0 authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
Browse files

drm/amd/display: use min disp and dpp clk debug option for dcn2 



This allows to set a minimum display and dpp clock on dcn2+ HW
by adjusting clocks used for dml calculations.

Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarLeo Li <sunpeng.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 39bca359

drivers/gpu/drm/amd/display/dc/dc.h

+1 −0
Original line number Diff line number Diff line
@@ -344,6 +344,7 @@ struct dc_debug_options { 
	bool disable_pplib_wm_range;

	enum wm_report_mode pplib_wm_report_mode;

	unsigned int min_disp_clk_khz;

	unsigned int min_dpp_clk_khz;

	int sr_exit_time_dpm0_ns;

	int sr_enter_plus_exit_time_dpm0_ns;

	int sr_exit_time_ns;

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

+4 −4
Original line number Diff line number Diff line
@@ -2170,10 +2170,6 @@ bool dcn20_fast_validate_bw( 
		}

		if (force_split && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1)

			context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2;

		if (dc->config.forced_clocks == true) {

			context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] =

					context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;

		}

		if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {

			hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, dc->res_pool, pipe);

			ASSERT(hsplit_pipe);
@@ -2293,6 +2289,10 @@ void dcn20_calculate_wm( 
				pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;

				pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;

			}

			if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)

				pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;

			if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)

				pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;



			pipe_cnt++;

		}

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