drm/i915/gen8: Add gen8_init_workarounds for common WA (e9a64ada) · Commits · 戴 / test

WA in this function should be ordered based on register address. The following order is suggested (Ville), instpm mi_mode row chicken half slice chicken common slice chicken hdc chicken cache_mode_0 cache_mode_1 gt_mode Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:

Arun Siluvery <arun.siluvery@linux.intel.com> Reviewed-by:

Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:

Daniel Vetter <daniel.vetter@ffwll.ch>

drivers/gpu/drm/i915/intel_ringbuffer.c

+16 −0

Original line number	Diff line number	Diff line
		@@ -800,11 +800,22 @@ static int wa_add(struct drm_i915_private *dev_priv,

		#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)

		static int gen8_init_workarounds(struct intel_engine_cs *ring)
		{

		return 0;
		}

		static int bdw_init_workarounds(struct intel_engine_cs *ring)
		{
		int ret;
		struct drm_device *dev = ring->dev;
		struct drm_i915_private *dev_priv = dev->dev_private;

		ret = gen8_init_workarounds(ring);
		if (ret)
		return ret;

		WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);

		/* WaDisableAsyncFlipPerfMode:bdw */
		@@ -868,9 +879,14 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)

		static int chv_init_workarounds(struct intel_engine_cs *ring)
		{
		int ret;
		struct drm_device *dev = ring->dev;
		struct drm_i915_private *dev_priv = dev->dev_private;

		ret = gen8_init_workarounds(ring);
		if (ret)
		return ret;

		WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);

		/* WaDisableAsyncFlipPerfMode:chv */

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