Commit e9a2ce13 authored by Archit Taneja's avatar Archit Taneja Committed by Rob Clark
Browse files

drm/msm/hdmi: Update generated headers for HDMI 8996 PHY 



Adds HDMI 8996 PHY offsets. The offsets are divided into 3 parts:
- Core HDMI PHY registers
- HDMI PLL registers (part of QSERDES block)
- HDMI TX lane registers (part of QSERDES block)

Signed-off-by: default avatarArchit Taneja <architt@codeaurora.org>
Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
parent 568be320

drivers/gpu/drm/msm/hdmi/hdmi.xml.h

+498 −2
Original line number Diff line number Diff line
@@ -8,10 +8,10 @@ http://github.com/freedreno/envytools/ 
git clone https://github.com/freedreno/envytools.git



The rules-ng-ng source files this header was generated from are:

- /local/mnt/workspace/source_trees/envytools/rnndb/../rnndb/hdmi/hdmi.xml  (  28770 bytes, from 2015-11-03 11:09:10)

- /local/mnt/workspace/source_trees/envytools/rnndb/../rnndb/hdmi/hdmi.xml  (  41472 bytes, from 2016-01-08 08:20:42)

- /local/mnt/workspace/source_trees/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2015-02-09 03:18:10)



Copyright (C) 2013-2015 by the following authors:

Copyright (C) 2013-2016 by the following authors:

- Rob Clark <robdclark@gmail.com> (robclark)



Permission is hereby granted, free of charge, to any person obtaining
@@ -834,5 +834,501 @@ static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val) 


#define REG_HDMI_28nm_PHY_PLL_DEBUG_BUS_SEL			0x000000a0



#define REG_HDMI_8996_PHY_CFG					0x00000000



#define REG_HDMI_8996_PHY_PD_CTL				0x00000004



#define REG_HDMI_8996_PHY_MODE					0x00000008



#define REG_HDMI_8996_PHY_MISR_CLEAR				0x0000000c



#define REG_HDMI_8996_PHY_TX0_TX1_BIST_CFG0			0x00000010



#define REG_HDMI_8996_PHY_TX0_TX1_BIST_CFG1			0x00000014



#define REG_HDMI_8996_PHY_TX0_TX1_PRBS_SEED_BYTE0		0x00000018



#define REG_HDMI_8996_PHY_TX0_TX1_PRBS_SEED_BYTE1		0x0000001c



#define REG_HDMI_8996_PHY_TX0_TX1_BIST_PATTERN0			0x00000020



#define REG_HDMI_8996_PHY_TX0_TX1_BIST_PATTERN1			0x00000024



#define REG_HDMI_8996_PHY_TX2_TX3_BIST_CFG0			0x00000028



#define REG_HDMI_8996_PHY_TX2_TX3_BIST_CFG1			0x0000002c



#define REG_HDMI_8996_PHY_TX2_TX3_PRBS_SEED_BYTE0		0x00000030



#define REG_HDMI_8996_PHY_TX2_TX3_PRBS_SEED_BYTE1		0x00000034



#define REG_HDMI_8996_PHY_TX2_TX3_BIST_PATTERN0			0x00000038



#define REG_HDMI_8996_PHY_TX2_TX3_BIST_PATTERN1			0x0000003c



#define REG_HDMI_8996_PHY_DEBUG_BUS_SEL				0x00000040



#define REG_HDMI_8996_PHY_TXCAL_CFG0				0x00000044



#define REG_HDMI_8996_PHY_TXCAL_CFG1				0x00000048



#define REG_HDMI_8996_PHY_TX0_TX1_LANE_CTL			0x0000004c



#define REG_HDMI_8996_PHY_TX2_TX3_LANE_CTL			0x00000050



#define REG_HDMI_8996_PHY_LANE_BIST_CONFIG			0x00000054



#define REG_HDMI_8996_PHY_CLOCK					0x00000058



#define REG_HDMI_8996_PHY_MISC1					0x0000005c



#define REG_HDMI_8996_PHY_MISC2					0x00000060



#define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS0			0x00000064



#define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS1			0x00000068



#define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS2			0x0000006c



#define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS0			0x00000070



#define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS1			0x00000074



#define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS2			0x00000078



#define REG_HDMI_8996_PHY_PRE_MISR_STATUS0			0x0000007c



#define REG_HDMI_8996_PHY_PRE_MISR_STATUS1			0x00000080



#define REG_HDMI_8996_PHY_PRE_MISR_STATUS2			0x00000084



#define REG_HDMI_8996_PHY_PRE_MISR_STATUS3			0x00000088



#define REG_HDMI_8996_PHY_POST_MISR_STATUS0			0x0000008c



#define REG_HDMI_8996_PHY_POST_MISR_STATUS1			0x00000090



#define REG_HDMI_8996_PHY_POST_MISR_STATUS2			0x00000094



#define REG_HDMI_8996_PHY_POST_MISR_STATUS3			0x00000098



#define REG_HDMI_8996_PHY_STATUS				0x0000009c



#define REG_HDMI_8996_PHY_MISC3_STATUS				0x000000a0



#define REG_HDMI_8996_PHY_MISC4_STATUS				0x000000a4



#define REG_HDMI_8996_PHY_DEBUG_BUS0				0x000000a8



#define REG_HDMI_8996_PHY_DEBUG_BUS1				0x000000ac



#define REG_HDMI_8996_PHY_DEBUG_BUS2				0x000000b0



#define REG_HDMI_8996_PHY_DEBUG_BUS3				0x000000b4



#define REG_HDMI_8996_PHY_PHY_REVISION_ID0			0x000000b8



#define REG_HDMI_8996_PHY_PHY_REVISION_ID1			0x000000bc



#define REG_HDMI_8996_PHY_PHY_REVISION_ID2			0x000000c0



#define REG_HDMI_8996_PHY_PHY_REVISION_ID3			0x000000c4



#define REG_HDMI_PHY_QSERDES_COM_ATB_SEL1			0x00000000



#define REG_HDMI_PHY_QSERDES_COM_ATB_SEL2			0x00000004



#define REG_HDMI_PHY_QSERDES_COM_FREQ_UPDATE			0x00000008



#define REG_HDMI_PHY_QSERDES_COM_BG_TIMER			0x0000000c



#define REG_HDMI_PHY_QSERDES_COM_SSC_EN_CENTER			0x00000010



#define REG_HDMI_PHY_QSERDES_COM_SSC_ADJ_PER1			0x00000014



#define REG_HDMI_PHY_QSERDES_COM_SSC_ADJ_PER2			0x00000018



#define REG_HDMI_PHY_QSERDES_COM_SSC_PER1			0x0000001c



#define REG_HDMI_PHY_QSERDES_COM_SSC_PER2			0x00000020



#define REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE1			0x00000024



#define REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE2			0x00000028



#define REG_HDMI_PHY_QSERDES_COM_POST_DIV			0x0000002c



#define REG_HDMI_PHY_QSERDES_COM_POST_DIV_MUX			0x00000030



#define REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN		0x00000034



#define REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1			0x00000038



#define REG_HDMI_PHY_QSERDES_COM_SYS_CLK_CTRL			0x0000003c



#define REG_HDMI_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE		0x00000040



#define REG_HDMI_PHY_QSERDES_COM_PLL_EN				0x00000044



#define REG_HDMI_PHY_QSERDES_COM_PLL_IVCO			0x00000048



#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0		0x0000004c



#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0		0x00000050



#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0		0x00000054



#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE1		0x00000058



#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE1		0x0000005c



#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE1		0x00000060



#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE2		0x00000064



#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD0			0x00000064



#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE2		0x00000068



#define REG_HDMI_PHY_QSERDES_COM_EP_CLOCK_DETECT_CTRL		0x00000068



#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE2		0x0000006c



#define REG_HDMI_PHY_QSERDES_COM_SYSCLK_DET_COMP_STATUS		0x0000006c



#define REG_HDMI_PHY_QSERDES_COM_BG_TRIM			0x00000070



#define REG_HDMI_PHY_QSERDES_COM_CLK_EP_DIV			0x00000074



#define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE0			0x00000078



#define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE1			0x0000007c



#define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE2			0x00000080



#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD1			0x00000080



#define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE0		0x00000084



#define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE1		0x00000088



#define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE2		0x0000008c



#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD2			0x0000008c



#define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE0		0x00000090



#define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE1		0x00000094



#define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE2		0x00000098



#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD3			0x00000098



#define REG_HDMI_PHY_QSERDES_COM_PLL_CNTRL			0x0000009c



#define REG_HDMI_PHY_QSERDES_COM_PHASE_SEL_CTRL			0x000000a0



#define REG_HDMI_PHY_QSERDES_COM_PHASE_SEL_DC			0x000000a4



#define REG_HDMI_PHY_QSERDES_COM_CORE_CLK_IN_SYNC_SEL		0x000000a8



#define REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CTRL_BY_PSM		0x000000a8



#define REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL			0x000000ac



#define REG_HDMI_PHY_QSERDES_COM_CML_SYSCLK_SEL			0x000000b0



#define REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL			0x000000b4



#define REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL2			0x000000b8



#define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CTRL			0x000000bc



#define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CTRL2			0x000000c0



#define REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM		0x000000c4



#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_EN			0x000000c8



#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_CFG			0x000000cc



#define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE0		0x000000d0



#define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE1		0x000000d4



#define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE2		0x000000d8



#define REG_HDMI_PHY_QSERDES_COM_VCOCAL_DEADMAN_CTRL		0x000000d8



#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0		0x000000dc



#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0		0x000000e0



#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0		0x000000e4



#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE1		0x000000e8



#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE1		0x000000ec



#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE1		0x000000f0



#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE2		0x000000f4



#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MINVAL1		0x000000f4



#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE2		0x000000f8



#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MINVAL2		0x000000f8



#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE2		0x000000fc



#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD4			0x000000fc



#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_INITVAL		0x00000100



#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_EN			0x00000104



#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0		0x00000108



#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0		0x0000010c



#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE1		0x00000110



#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE1		0x00000114



#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE2		0x00000118



#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAXVAL1		0x00000118



#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE2		0x0000011c



#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAXVAL2		0x0000011c



#define REG_HDMI_PHY_QSERDES_COM_RES_TRIM_CONTROL2		0x00000120



#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_CTRL			0x00000124



#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAP			0x00000128



#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE0		0x0000012c



#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE0		0x00000130



#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE1		0x00000134



#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE1		0x00000138



#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE2		0x0000013c



#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_INITVAL1		0x0000013c



#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE2		0x00000140



#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_INITVAL2		0x00000140



#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_TIMER1		0x00000144



#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_TIMER2		0x00000148



#define REG_HDMI_PHY_QSERDES_COM_SAR				0x0000014c



#define REG_HDMI_PHY_QSERDES_COM_SAR_CLK			0x00000150



#define REG_HDMI_PHY_QSERDES_COM_SAR_CODE_OUT_STATUS		0x00000154



#define REG_HDMI_PHY_QSERDES_COM_SAR_CODE_READY_STATUS		0x00000158



#define REG_HDMI_PHY_QSERDES_COM_CMN_STATUS			0x0000015c



#define REG_HDMI_PHY_QSERDES_COM_RESET_SM_STATUS		0x00000160



#define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CODE_STATUS		0x00000164



#define REG_HDMI_PHY_QSERDES_COM_PLLCAL_CODE1_STATUS		0x00000168



#define REG_HDMI_PHY_QSERDES_COM_PLLCAL_CODE2_STATUS		0x0000016c



#define REG_HDMI_PHY_QSERDES_COM_BG_CTRL			0x00000170



#define REG_HDMI_PHY_QSERDES_COM_CLK_SELECT			0x00000174



#define REG_HDMI_PHY_QSERDES_COM_HSCLK_SEL			0x00000178



#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_BINCODE_STATUS	0x0000017c



#define REG_HDMI_PHY_QSERDES_COM_PLL_ANALOG			0x00000180



#define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV			0x00000184



#define REG_HDMI_PHY_QSERDES_COM_SW_RESET			0x00000188



#define REG_HDMI_PHY_QSERDES_COM_CORE_CLK_EN			0x0000018c



#define REG_HDMI_PHY_QSERDES_COM_C_READY_STATUS			0x00000190



#define REG_HDMI_PHY_QSERDES_COM_CMN_CONFIG			0x00000194



#define REG_HDMI_PHY_QSERDES_COM_CMN_RATE_OVERRIDE		0x00000198



#define REG_HDMI_PHY_QSERDES_COM_SVS_MODE_CLK_SEL		0x0000019c



#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS0			0x000001a0



#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS1			0x000001a4



#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS2			0x000001a8



#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS3			0x000001ac



#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS_SEL			0x000001b0



#define REG_HDMI_PHY_QSERDES_COM_CMN_MISC1			0x000001b4



#define REG_HDMI_PHY_QSERDES_COM_CMN_MISC2			0x000001b8



#define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV_MODE1		0x000001bc



#define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV_MODE2		0x000001c0



#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD5			0x000001c4



#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_MODE_LANENO		0x00000000



#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_INVERT			0x00000004



#define REG_HDMI_PHY_QSERDES_TX_LX_CLKBUF_ENABLE		0x00000008



#define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_ONE		0x0000000c



#define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_TWO		0x00000010



#define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_THREE		0x00000014



#define REG_HDMI_PHY_QSERDES_TX_LX_TX_EMP_POST1_LVL		0x00000018



#define REG_HDMI_PHY_QSERDES_TX_LX_TX_POST2_EMPH		0x0000001c



#define REG_HDMI_PHY_QSERDES_TX_LX_TX_BOOST_LVL_UP_DN		0x00000020



#define REG_HDMI_PHY_QSERDES_TX_LX_HP_PD_ENABLES		0x00000024



#define REG_HDMI_PHY_QSERDES_TX_LX_TX_IDLE_LVL_LARGE_AMP	0x00000028



#define REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL			0x0000002c



#define REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL_OFFSET		0x00000030



#define REG_HDMI_PHY_QSERDES_TX_LX_RESET_TSYNC_EN		0x00000034



#define REG_HDMI_PHY_QSERDES_TX_LX_PRE_STALL_LDO_BOOST_EN	0x00000038



#define REG_HDMI_PHY_QSERDES_TX_LX_TX_BAND			0x0000003c



#define REG_HDMI_PHY_QSERDES_TX_LX_SLEW_CNTL			0x00000040



#define REG_HDMI_PHY_QSERDES_TX_LX_INTERFACE_SELECT		0x00000044



#define REG_HDMI_PHY_QSERDES_TX_LX_LPB_EN			0x00000048



#define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_TX		0x0000004c



#define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_RX		0x00000050



#define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_OFFSET		0x00000054



#define REG_HDMI_PHY_QSERDES_TX_LX_PERL_LENGTH1			0x00000058



#define REG_HDMI_PHY_QSERDES_TX_LX_PERL_LENGTH2			0x0000005c



#define REG_HDMI_PHY_QSERDES_TX_LX_SERDES_BYP_EN_OUT		0x00000060



#define REG_HDMI_PHY_QSERDES_TX_LX_DEBUG_BUS_SEL		0x00000064



#define REG_HDMI_PHY_QSERDES_TX_LX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN	0x00000068



#define REG_HDMI_PHY_QSERDES_TX_LX_TX_POL_INV			0x0000006c



#define REG_HDMI_PHY_QSERDES_TX_LX_PARRATE_REC_DETECT_IDLE_EN	0x00000070



#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN1		0x00000074



#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN2		0x00000078



#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN3		0x0000007c



#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN4		0x00000080



#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN5		0x00000084



#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN6		0x00000088



#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN7		0x0000008c



#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN8		0x00000090



#define REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE			0x00000094



#define REG_HDMI_PHY_QSERDES_TX_LX_IDAC_CAL_LANE_MODE		0x00000098



#define REG_HDMI_PHY_QSERDES_TX_LX_IDAC_CAL_LANE_MODE_CONFIGURATION	0x0000009c



#define REG_HDMI_PHY_QSERDES_TX_LX_ATB_SEL1			0x000000a0



#define REG_HDMI_PHY_QSERDES_TX_LX_ATB_SEL2			0x000000a4



#define REG_HDMI_PHY_QSERDES_TX_LX_RCV_DETECT_LVL		0x000000a8



#define REG_HDMI_PHY_QSERDES_TX_LX_RCV_DETECT_LVL_2		0x000000ac



#define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED1			0x000000b0



#define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED2			0x000000b4



#define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED3			0x000000b8



#define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED4			0x000000bc



#define REG_HDMI_PHY_QSERDES_TX_LX_RESET_GEN			0x000000c0



#define REG_HDMI_PHY_QSERDES_TX_LX_RESET_GEN_MUXES		0x000000c4



#define REG_HDMI_PHY_QSERDES_TX_LX_TRAN_DRVR_EMP_EN		0x000000c8



#define REG_HDMI_PHY_QSERDES_TX_LX_TX_INTERFACE_MODE		0x000000cc



#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_CTRL			0x000000d0



#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_ENCODED_OR_DATA		0x000000d4



#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_1_DIVIDER_BAND2	0x000000d8



#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_2_DIVIDER_BAND2	0x000000dc



#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_3_DIVIDER_BAND2	0x000000e0



#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_4_DIVIDER_BAND2	0x000000e4



#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_1_DIVIDER_BAND0_1	0x000000e8



#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_2_DIVIDER_BAND0_1	0x000000ec



#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_3_DIVIDER_BAND0_1	0x000000f0



#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_4_DIVIDER_BAND0_1	0x000000f4



#define REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL1			0x000000f8



#define REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL2			0x000000fc



#define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV_CNTL	0x00000100



#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_STATUS			0x00000104



#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_ERROR_COUNT1		0x00000108



#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_ERROR_COUNT2		0x0000010c



#define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV		0x00000110





#endif /* HDMI_XML */

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