Commit e996e208 authored Sep 15, 2016 by Chen-Yu Tsai Committed by Maxime Ripard Sep 18, 2016

drm/sun4i: dotclock: Fix clock rate read back calcation



When reading back the divider set in the register, we mask off the
bits that aren't part of the divider. Unfortunately the mask used
here was not converted from the field width.

Fix this by converting the field width to a proper bit mask.

Fixes: 9026e0d1 ("drm: Add Allwinner A10 Display Engine support")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

parent 9a8aa939

drivers/gpu/drm/sun4i/sun4i_dotclock.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -62,7 +62,7 @@ static unsigned long sun4i_dclk_recalc_rate(struct clk_hw *hw,
	regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val);		regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val);

	val >>= SUN4I_TCON0_DCLK_DIV_SHIFT;		val >>= SUN4I_TCON0_DCLK_DIV_SHIFT;
	val &= SUN4I_TCON0_DCLK_DIV_WIDTH;		val &= (1 << SUN4I_TCON0_DCLK_DIV_WIDTH) - 1;

	if (!val)		if (!val)
	val = 1;		val = 1;

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