Merge branches 'arm/omap', 'arm/exynos', 'arm/smmu', 'arm/mediatek',...

			Note that using this option lowers the security

			provided by tboot because it makes the system

			vulnerable to DMA attacks.

		nobounce [Default off]

			Disable bounce buffer for unstrusted devices such as

			the Thunderbolt devices. This will treat the untrusted

			devices as the trusted ones, hence might expose security

			risks of DMA attacks.

	intel_idle.max_cstate=	[KNL,HW,ACPI,X86]

			0	disables intel_idle and fall back on acpi_idle.

			  synchronously.

	iommu.passthrough=

			[ARM64] Configure DMA to bypass the IOMMU by default.

			[ARM64, X86] Configure DMA to bypass the IOMMU by default.

			Format: { "0" | "1" }

			0 - Use IOMMU translation for DMA.

			1 - Bypass the IOMMU for DMA.

               |

              m4u (Multimedia Memory Management Unit)

               |

          +--------+

          |        |

      gals0-rx   gals1-rx    (Global Async Local Sync rx)

          |        |

          |        |

      gals0-tx   gals1-tx    (Global Async Local Sync tx)

          |        |          Some SoCs may have GALS.

          +--------+

               |

           SMI Common(Smart Multimedia Interface Common)

               |

       +----------------+-------

       |                |

       |             gals-rx        There may be GALS in some larbs.

       |                |

       |                |

       |             gals-tx

       |                |

   SMI larb0        SMI larb1   ... SoCs have several SMI local arbiter(larb).

   (display)         (vdec)

like display, video decode, and camera. And there are different ports

in each larb. Take a example, There are many ports like MC, PP, VLD in the

video decode local arbiter, all these ports are according to the video HW.

  In some SoCs, there may be a GALS(Global Async Local Sync) module between

smi-common and m4u, and additional GALS module between smi-larb and

smi-common. GALS can been seen as a "asynchronous fifo" which could help

synchronize for the modules in different clock frequency.

Required properties:

- compatible : must be one of the following string:

	"mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses

						     generation one m4u HW.

	"mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW.

	"mediatek,mt8183-m4u" for mt8183 which uses generation two m4u HW.

- reg : m4u register base and size.

- interrupts : the interrupt of m4u.

- clocks : must contain one entry for each clock-names.

- clock-names : must be "bclk", It is the block clock of m4u.

- clock-names : Only 1 optional clock:

  - "bclk": the block clock of m4u.

  Here is the list which require this "bclk":

  - mt2701, mt2712, mt7623 and mt8173.

  Note that m4u use the EMI clock which always has been enabled before kernel

  if there is no this "bclk".

- mediatek,larbs : List of phandle to the local arbiters in the current Socs.

	Refer to bindings/memory-controllers/mediatek,smi-larb.txt. It must sort

	according to the local arbiter index, like larb0, larb1, larb2...

- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW.

	Specifies the mtk_m4u_id as defined in

	dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623

	dt-binding/memory/mt2712-larb-port.h for mt2712, and

	dt-binding/memory/mt8173-larb-port.h for mt8173.

	dt-binding/memory/mt2712-larb-port.h for mt2712,

	dt-binding/memory/mt8173-larb-port.h for mt8173, and

	dt-binding/memory/mt8183-larb-port.h for mt8183.

Example:

	iommu: iommu@10205000 {

The hardware block diagram please check bindings/iommu/mediatek,iommu.txt

Mediatek SMI have two generations of HW architecture, mt2712 and mt8173 use

the second generation of SMI HW while mt2701 uses the first generation HW of

SMI.

Mediatek SMI have two generations of HW architecture, here is the list

which generation the SoCs use:

generation 1: mt2701 and mt7623.

generation 2: mt2712, mt8173 and mt8183.

There's slight differences between the two SMI, for generation 2, the

register which control the iommu port is at each larb's register base. But

	"mediatek,mt2712-smi-common"

	"mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"

	"mediatek,mt8173-smi-common"

	"mediatek,mt8183-smi-common"

- reg : the register and size of the SMI block.

- power-domains : a phandle to the power domain of this local arbiter.

- clocks : Must contain an entry for each entry in clock-names.

	    They may be the same if both source clocks are the same.

  - "async" : asynchronous clock, it help transform the smi clock into the emi

	      clock domain, this clock is only needed by generation 1 smi HW.

  and these 2 option clocks for generation 2 smi HW:

  - "gals0": the path0 clock of GALS(Global Async Local Sync).

  - "gals1": the path1 clock of GALS(Global Async Local Sync).

  Here is the list which has this GALS: mt8183.

Example:

	smi_common: smi@14022000 {

		"mediatek,mt2712-smi-larb"

		"mediatek,mt7623-smi-larb", "mediatek,mt2701-smi-larb"

		"mediatek,mt8173-smi-larb"

		"mediatek,mt8183-smi-larb"

- reg : the register and size of this local arbiter.

- mediatek,smi : a phandle to the smi_common node.

- power-domains : a phandle to the power domain of this local arbiter.

  - "apb" : Advanced Peripheral Bus clock, It's the clock for setting

	    the register.

  - "smi" : It's the clock for transfer data and command.

  and this optional clock name:

  - "gals": the clock for GALS(Global Async Local Sync).

  Here is the list which has this GALS: mt8183.

Required property for mt2701, mt2712 and mt7623:

- mediatek,larb-id :the hardware id of this larb.

R:	Robin Murphy <robin.murphy@arm.com>

L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

S:	Maintained

F:	drivers/iommu/arm-smmu.c

F:	drivers/iommu/arm-smmu-v3.c

F:	drivers/iommu/arm-smmu*

F:	drivers/iommu/io-pgtable-arm.c

F:	drivers/iommu/io-pgtable-arm-v7s.c