Commit e9501b97 authored Sep 16, 2020 by Zhao Qiang Committed by Stephen Boyd Oct 13, 2020

clk: qoriq: modify MAX_PLL_DIV to 32



On LS2088A, Watchdog need clk divided by 32,
so modify MAX_PLL_DIV to 32

Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Link: https://lore.kernel.org/r/20200916030311.17280-1-qiang.zhao@nxp.com


Signed-off-by: Stephen Boyd <sboyd@kernel.org>

parent 9123e3a7

drivers/clk/clk-qoriq.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -31,7 +31,7 @@
		#define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
		#define CGB_PLL1 4
		#define CGB_PLL2 5
		#define MAX_PLL_DIV 16
		#define MAX_PLL_DIV 32

		struct clockgen_pll_div {
		struct clk *clk;

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