Commit e94bda14 authored by Lucas De Marchi's avatar Lucas De Marchi
Browse files

drm/i915/tgl: Add Wa_1608008084



Wa_1608008084 is an additional WA that applies to writes on FF_MODE2
register. We can't read it back either from CPU or GPU. Since the other
bits should be 0, recommendation to handle Wa_1604555607 is to actually
just write the timer value.

Do a write only and don't try to read it, neither before or after
the WA is applied.

Fixes: ff690b21 ("drm/i915/tgl: Implement Wa_1604555607")
Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200224191258.15668-1-lucas.demarchi@intel.com
parent 041be481
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+7 −12
Original line number Diff line number Diff line
@@ -580,24 +580,19 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
				     struct i915_wa_list *wal)
{
	u32 val;

	/* Wa_1409142259:tgl */
	WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
			  GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);

	/* Wa_1604555607:tgl */
	val = intel_uncore_read(engine->uncore, FF_MODE2);
	val &= ~FF_MODE2_TDS_TIMER_MASK;
	val |= FF_MODE2_TDS_TIMER_128;
	/*
	 * FIXME: FF_MODE2 register is not readable till TGL B0. We can
	 * enable verification of WA from the later steppings, which enables
	 * the read of FF_MODE2.
	 * Wa_1604555607:gen12 and Wa_1608008084:gen12
	 * FF_MODE2 register will return the wrong value when read. The default
	 * value for this register is zero for all fields and there are no bit
	 * masks. So instead of doing a RMW we should just write the TDS timer
	 * value for Wa_1604555607.
	 */
	wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
	       IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
			    FF_MODE2_TDS_TIMER_MASK);
	wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK,
	       FF_MODE2_TDS_TIMER_128, 0);
}

static void