Merge branch 'octeontx2-af-NPA-and-NIX-blocks-initialization' (e943d94e) · Commits · 戴 / test

drivers/net/ethernet/marvell/octeontx2/af/Makefile

+1 −1

Original line number	Diff line number	Diff line
		@@ -7,4 +7,4 @@ obj-$(CONFIG_OCTEONTX2_MBOX) += octeontx2_mbox.o
		obj-$(CONFIG_OCTEONTX2_AF) += octeontx2_af.o

		octeontx2_mbox-y := mbox.o
		octeontx2_af-y := cgx.o rvu.o rvu_cgx.o
		octeontx2_af-y := cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o

drivers/net/ethernet/marvell/octeontx2/af/cgx.c

+234 −10

Original line number	Diff line number	Diff line
		@@ -29,6 +29,7 @@
		* @wq_cmd_cmplt: waitq to keep the process blocked until cmd completion
		* @cmd_lock: Lock to serialize the command interface
		* @resp: command response
		* @link_info: link related information
		* @event_cb: callback for linkchange events
		* @cmd_pend: flag set before new command is started
		* flag cleared after command response is received
		@@ -40,6 +41,7 @@ struct lmac {
		wait_queue_head_t wq_cmd_cmplt;
		struct mutex cmd_lock;
		u64 resp;
		struct cgx_link_user_info link_info;
		struct cgx_event_cb event_cb;
		bool cmd_pend;
		struct cgx *cgx;
		@@ -58,6 +60,12 @@ struct cgx {

		static LIST_HEAD(cgx_list);

		/* Convert firmware speed encoding to user format(Mbps) */
		static u32 cgx_speed_mbps[CGX_LINK_SPEED_MAX];

		/* Convert firmware lmac type encoding to string */
		static char *cgx_lmactype_string[LMAC_MODE_MAX];

		/* Supported devices */
		static const struct pci_device_id cgx_id_table[] = {
		{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_CGX) },
		@@ -119,6 +127,177 @@ void *cgx_get_pdata(int cgx_id)
		}
		EXPORT_SYMBOL(cgx_get_pdata);

		/* Ensure the required lock for event queue(where asynchronous events are
		* posted) is acquired before calling this API. Else an asynchronous event(with
		* latest link status) can reach the destination before this function returns
		* and could make the link status appear wrong.
		*/
		int cgx_get_link_info(void *cgxd, int lmac_id,
		struct cgx_link_user_info *linfo)
		{
		struct lmac *lmac = lmac_pdata(lmac_id, cgxd);

		if (!lmac)
		return -ENODEV;

		*linfo = lmac->link_info;
		return 0;
		}
		EXPORT_SYMBOL(cgx_get_link_info);

		static u64 mac2u64 (u8 *mac_addr)
		{
		u64 mac = 0;
		int index;

		for (index = ETH_ALEN - 1; index >= 0; index--)
		mac \|= ((u64)mac_addr++) << (8 index);
		return mac;
		}

		int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr)
		{
		struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
		u64 cfg;

		/* copy 6bytes from macaddr */
		/* memcpy(&cfg, mac_addr, 6); */

		cfg = mac2u64 (mac_addr);

		cgx_write(cgx_dev, 0, (CGXX_CMRX_RX_DMAC_CAM0 + (lmac_id * 0x8)),
		cfg \| CGX_DMAC_CAM_ADDR_ENABLE \| ((u64)lmac_id << 49));

		cfg = cgx_read(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
		cfg \|= CGX_DMAC_CTL0_CAM_ENABLE;
		cgx_write(cgx_dev, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);

		return 0;
		}
		EXPORT_SYMBOL(cgx_lmac_addr_set);

		u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id)
		{
		struct cgx *cgx_dev = cgx_get_pdata(cgx_id);
		u64 cfg;

		cfg = cgx_read(cgx_dev, 0, CGXX_CMRX_RX_DMAC_CAM0 + lmac_id * 0x8);
		return cfg & CGX_RX_DMAC_ADR_MASK;
		}
		EXPORT_SYMBOL(cgx_lmac_addr_get);

		static inline u8 cgx_get_lmac_type(struct cgx *cgx, int lmac_id)
		{
		u64 cfg;

		cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG);
		return (cfg >> CGX_LMAC_TYPE_SHIFT) & CGX_LMAC_TYPE_MASK;
		}

		/* Configure CGX LMAC in internal loopback mode */
		int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable)
		{
		struct cgx *cgx = cgxd;
		u8 lmac_type;
		u64 cfg;

		if (!cgx \|\| lmac_id >= cgx->lmac_count)
		return -ENODEV;

		lmac_type = cgx_get_lmac_type(cgx, lmac_id);
		if (lmac_type == LMAC_MODE_SGMII \|\| lmac_type == LMAC_MODE_QSGMII) {
		cfg = cgx_read(cgx, lmac_id, CGXX_GMP_PCS_MRX_CTL);
		if (enable)
		cfg \|= CGXX_GMP_PCS_MRX_CTL_LBK;
		else
		cfg &= ~CGXX_GMP_PCS_MRX_CTL_LBK;
		cgx_write(cgx, lmac_id, CGXX_GMP_PCS_MRX_CTL, cfg);
		} else {
		cfg = cgx_read(cgx, lmac_id, CGXX_SPUX_CONTROL1);
		if (enable)
		cfg \|= CGXX_SPUX_CONTROL1_LBK;
		else
		cfg &= ~CGXX_SPUX_CONTROL1_LBK;
		cgx_write(cgx, lmac_id, CGXX_SPUX_CONTROL1, cfg);
		}
		return 0;
		}
		EXPORT_SYMBOL(cgx_lmac_internal_loopback);

		void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable)
		{
		struct cgx *cgx = cgx_get_pdata(cgx_id);
		u64 cfg = 0;

		if (!cgx)
		return;

		if (enable) {
		/* Enable promiscuous mode on LMAC */
		cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
		cfg &= ~(CGX_DMAC_CAM_ACCEPT \| CGX_DMAC_MCAST_MODE);
		cfg \|= CGX_DMAC_BCAST_MODE;
		cgx_write(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);

		cfg = cgx_read(cgx, 0,
		(CGXX_CMRX_RX_DMAC_CAM0 + lmac_id * 0x8));
		cfg &= ~CGX_DMAC_CAM_ADDR_ENABLE;
		cgx_write(cgx, 0,
		(CGXX_CMRX_RX_DMAC_CAM0 + lmac_id * 0x8), cfg);
		} else {
		/* Disable promiscuous mode */
		cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0);
		cfg \|= CGX_DMAC_CAM_ACCEPT \| CGX_DMAC_MCAST_MODE;
		cgx_write(cgx, lmac_id, CGXX_CMRX_RX_DMAC_CTL0, cfg);
		cfg = cgx_read(cgx, 0,
		(CGXX_CMRX_RX_DMAC_CAM0 + lmac_id * 0x8));
		cfg \|= CGX_DMAC_CAM_ADDR_ENABLE;
		cgx_write(cgx, 0,
		(CGXX_CMRX_RX_DMAC_CAM0 + lmac_id * 0x8), cfg);
		}
		}
		EXPORT_SYMBOL(cgx_lmac_promisc_config);

		int cgx_get_rx_stats(void cgxd, int lmac_id, int idx, u64 rx_stat)
		{
		struct cgx *cgx = cgxd;

		if (!cgx \|\| lmac_id >= cgx->lmac_count)
		return -ENODEV;
		rx_stat = cgx_read(cgx, lmac_id, CGXX_CMRX_RX_STAT0 + (idx 8));
		return 0;
		}
		EXPORT_SYMBOL(cgx_get_rx_stats);

		int cgx_get_tx_stats(void cgxd, int lmac_id, int idx, u64 tx_stat)
		{
		struct cgx *cgx = cgxd;

		if (!cgx \|\| lmac_id >= cgx->lmac_count)
		return -ENODEV;
		tx_stat = cgx_read(cgx, lmac_id, CGXX_CMRX_TX_STAT0 + (idx 8));
		return 0;
		}
		EXPORT_SYMBOL(cgx_get_tx_stats);

		int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable)
		{
		struct cgx *cgx = cgxd;
		u64 cfg;

		if (!cgx \|\| lmac_id >= cgx->lmac_count)
		return -ENODEV;

		cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG);
		if (enable)
		cfg \|= CMR_EN \| DATA_PKT_RX_EN \| DATA_PKT_TX_EN;
		else
		cfg &= ~(CMR_EN \| DATA_PKT_RX_EN \| DATA_PKT_TX_EN);
		cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg);
		return 0;
		}
		EXPORT_SYMBOL(cgx_lmac_rx_tx_enable);

		/* CGX Firmware interface low level support */
		static int cgx_fwi_cmd_send(u64 req, u64 resp, struct lmac lmac)
		{
		@@ -191,36 +370,79 @@ static inline int cgx_fwi_cmd_generic(u64 req, u64 *resp,
		return err;
		}

		static inline void cgx_link_usertable_init(void)
		{
		cgx_speed_mbps[CGX_LINK_NONE] = 0;
		cgx_speed_mbps[CGX_LINK_10M] = 10;
		cgx_speed_mbps[CGX_LINK_100M] = 100;
		cgx_speed_mbps[CGX_LINK_1G] = 1000;
		cgx_speed_mbps[CGX_LINK_2HG] = 2500;
		cgx_speed_mbps[CGX_LINK_5G] = 5000;
		cgx_speed_mbps[CGX_LINK_10G] = 10000;
		cgx_speed_mbps[CGX_LINK_20G] = 20000;
		cgx_speed_mbps[CGX_LINK_25G] = 25000;
		cgx_speed_mbps[CGX_LINK_40G] = 40000;
		cgx_speed_mbps[CGX_LINK_50G] = 50000;
		cgx_speed_mbps[CGX_LINK_100G] = 100000;

		cgx_lmactype_string[LMAC_MODE_SGMII] = "SGMII";
		cgx_lmactype_string[LMAC_MODE_XAUI] = "XAUI";
		cgx_lmactype_string[LMAC_MODE_RXAUI] = "RXAUI";
		cgx_lmactype_string[LMAC_MODE_10G_R] = "10G_R";
		cgx_lmactype_string[LMAC_MODE_40G_R] = "40G_R";
		cgx_lmactype_string[LMAC_MODE_QSGMII] = "QSGMII";
		cgx_lmactype_string[LMAC_MODE_25G_R] = "25G_R";
		cgx_lmactype_string[LMAC_MODE_50G_R] = "50G_R";
		cgx_lmactype_string[LMAC_MODE_100G_R] = "100G_R";
		cgx_lmactype_string[LMAC_MODE_USXGMII] = "USXGMII";
		}

		static inline void link_status_user_format(u64 lstat,
		struct cgx_link_user_info *linfo,
		struct cgx *cgx, u8 lmac_id)
		{
		char *lmac_string;

		linfo->link_up = FIELD_GET(RESP_LINKSTAT_UP, lstat);
		linfo->full_duplex = FIELD_GET(RESP_LINKSTAT_FDUPLEX, lstat);
		linfo->speed = cgx_speed_mbps[FIELD_GET(RESP_LINKSTAT_SPEED, lstat)];
		linfo->lmac_type_id = cgx_get_lmac_type(cgx, lmac_id);
		lmac_string = cgx_lmactype_string[linfo->lmac_type_id];
		strncpy(linfo->lmac_type, lmac_string, LMACTYPE_STR_LEN - 1);
		}

		/* Hardware event handlers */
		static inline void cgx_link_change_handler(u64 lstat,
		struct lmac *lmac)
		{
		struct cgx_link_user_info *linfo;
		struct cgx *cgx = lmac->cgx;
		struct cgx_link_event event;
		struct device *dev;
		int err_type;

		dev = &cgx->pdev->dev;

		event.lstat.link_up = FIELD_GET(RESP_LINKSTAT_UP, lstat);
		event.lstat.full_duplex = FIELD_GET(RESP_LINKSTAT_FDUPLEX, lstat);
		event.lstat.speed = FIELD_GET(RESP_LINKSTAT_SPEED, lstat);
		event.lstat.err_type = FIELD_GET(RESP_LINKSTAT_ERRTYPE, lstat);
		link_status_user_format(lstat, &event.link_uinfo, cgx, lmac->lmac_id);
		err_type = FIELD_GET(RESP_LINKSTAT_ERRTYPE, lstat);

		event.cgx_id = cgx->cgx_id;
		event.lmac_id = lmac->lmac_id;

		/* update the local copy of link status */
		lmac->link_info = event.link_uinfo;
		linfo = &lmac->link_info;

		if (!lmac->event_cb.notify_link_chg) {
		dev_dbg(dev, "cgx port %d:%d Link change handler null",
		cgx->cgx_id, lmac->lmac_id);
		if (event.lstat.err_type != CGX_ERR_NONE) {
		if (err_type != CGX_ERR_NONE) {
		dev_err(dev, "cgx port %d:%d Link error %d\n",
		cgx->cgx_id, lmac->lmac_id,
		event.lstat.err_type);
		cgx->cgx_id, lmac->lmac_id, err_type);
		}
		dev_info(dev, "cgx port %d:%d Link status %s, speed %x\n",
		dev_info(dev, "cgx port %d:%d Link is %s %d Mbps\n",
		cgx->cgx_id, lmac->lmac_id,
		event.lstat.link_up ? "UP" : "DOWN",
		event.lstat.speed);
		linfo->link_up ? "UP" : "DOWN", linfo->speed);
		return;
		}

		@@ -448,6 +670,8 @@ static int cgx_probe(struct pci_dev pdev, const struct pci_device_id id)
		list_add(&cgx->cgx_list, &cgx_list);
		cgx->cgx_id = cgx_get_cgx_cnt() - 1;

		cgx_link_usertable_init();

		err = cgx_lmac_init(cgx);
		if (err)
		goto err_release_lmac;

drivers/net/ethernet/marvell/octeontx2/af/cgx.h

+46 −1

Original line number	Diff line number	Diff line
		@@ -11,6 +11,7 @@
		#ifndef CGX_H
		#define CGX_H

		#include "mbox.h"
		#include "cgx_fw_if.h"

		/* PCI device IDs */
		@@ -24,14 +25,35 @@
		#define CGX_OFFSET(x) ((x) * MAX_LMAC_PER_CGX)

		/* Registers */
		#define CGXX_CMRX_CFG 0x00
		#define CMR_EN BIT_ULL(55)
		#define DATA_PKT_TX_EN BIT_ULL(53)
		#define DATA_PKT_RX_EN BIT_ULL(54)
		#define CGX_LMAC_TYPE_SHIFT 40
		#define CGX_LMAC_TYPE_MASK 0xF
		#define CGXX_CMRX_INT 0x040
		#define FW_CGX_INT BIT_ULL(1)
		#define CGXX_CMRX_INT_ENA_W1S 0x058
		#define CGXX_CMRX_RX_ID_MAP 0x060
		#define CGXX_CMRX_RX_STAT0 0x070
		#define CGXX_CMRX_RX_LMACS 0x128
		#define CGXX_CMRX_RX_DMAC_CTL0 0x1F8
		#define CGX_DMAC_CTL0_CAM_ENABLE BIT_ULL(3)
		#define CGX_DMAC_CAM_ACCEPT BIT_ULL(3)
		#define CGX_DMAC_MCAST_MODE BIT_ULL(1)
		#define CGX_DMAC_BCAST_MODE BIT_ULL(0)
		#define CGXX_CMRX_RX_DMAC_CAM0 0x200
		#define CGX_DMAC_CAM_ADDR_ENABLE BIT_ULL(48)
		#define CGXX_CMRX_RX_DMAC_CAM1 0x400
		#define CGX_RX_DMAC_ADR_MASK GENMASK_ULL(47, 0)
		#define CGXX_CMRX_TX_STAT0 0x700
		#define CGXX_SCRATCH0_REG 0x1050
		#define CGXX_SCRATCH1_REG 0x1058
		#define CGX_CONST 0x2000
		#define CGXX_SPUX_CONTROL1 0x10000
		#define CGXX_SPUX_CONTROL1_LBK BIT_ULL(14)
		#define CGXX_GMP_PCS_MRX_CTL 0x30000
		#define CGXX_GMP_PCS_MRX_CTL_LBK BIT_ULL(14)

		#define CGX_COMMAND_REG CGXX_SCRATCH1_REG
		#define CGX_EVENT_REG CGXX_SCRATCH0_REG
		@@ -40,8 +62,22 @@
		#define CGX_NVEC 37
		#define CGX_LMAC_FWI 0

		enum LMAC_TYPE {
		LMAC_MODE_SGMII = 0,
		LMAC_MODE_XAUI = 1,
		LMAC_MODE_RXAUI = 2,
		LMAC_MODE_10G_R = 3,
		LMAC_MODE_40G_R = 4,
		LMAC_MODE_QSGMII = 6,
		LMAC_MODE_25G_R = 7,
		LMAC_MODE_50G_R = 8,
		LMAC_MODE_100G_R = 9,
		LMAC_MODE_USXGMII = 10,
		LMAC_MODE_MAX,
		};

		struct cgx_link_event {
		struct cgx_lnk_sts lstat;
		struct cgx_link_user_info link_uinfo;
		u8 cgx_id;
		u8 lmac_id;
		};
		@@ -62,4 +98,13 @@ int cgx_get_cgx_cnt(void);
		int cgx_get_lmac_cnt(void *cgxd);
		void *cgx_get_pdata(int cgx_id);
		int cgx_lmac_evh_register(struct cgx_event_cb cb, void cgxd, int lmac_id);
		int cgx_get_tx_stats(void cgxd, int lmac_id, int idx, u64 tx_stat);
		int cgx_get_rx_stats(void cgxd, int lmac_id, int idx, u64 rx_stat);
		int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable);
		int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr);
		u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id);
		void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable);
		int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable);
		int cgx_get_link_info(void *cgxd, int lmac_id,
		struct cgx_link_user_info *linfo);
		#endif /* CGX_H */

drivers/net/ethernet/marvell/octeontx2/af/common.h

0 → 100644

+161 −0

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: GPL-2.0
		* Marvell OcteonTx2 RVU Admin Function driver
		*
		* Copyright (C) 2018 Marvell International Ltd.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 as
		* published by the Free Software Foundation.
		*/

		#ifndef COMMON_H
		#define COMMON_H

		#include "rvu_struct.h"

		#define OTX2_ALIGN 128 /* Align to cacheline */

		#define Q_SIZE_16 0ULL /* 16 entries */
		#define Q_SIZE_64 1ULL /* 64 entries */
		#define Q_SIZE_256 2ULL
		#define Q_SIZE_1K 3ULL
		#define Q_SIZE_4K 4ULL
		#define Q_SIZE_16K 5ULL
		#define Q_SIZE_64K 6ULL
		#define Q_SIZE_256K 7ULL
		#define Q_SIZE_1M 8ULL /* Million entries */
		#define Q_SIZE_MIN Q_SIZE_16
		#define Q_SIZE_MAX Q_SIZE_1M

		#define Q_COUNT(x) (16ULL << (2 * x))
		#define Q_SIZE(x, n) ((ilog2(x) - (n)) / 2)

		/* Admin queue info */

		/* Since we intend to add only one instruction at a time,
		* keep queue size to it's minimum.
		*/
		#define AQ_SIZE Q_SIZE_16
		/* HW head & tail pointer mask */
		#define AQ_PTR_MASK 0xFFFFF

		struct qmem {
		void *base;
		dma_addr_t iova;
		int alloc_sz;
		u8 entry_sz;
		u8 align;
		u32 qsize;
		};

		static inline int qmem_alloc(struct device dev, struct qmem *q,
		int qsize, int entry_sz)
		{
		struct qmem *qmem;
		int aligned_addr;

		if (!qsize)
		return -EINVAL;

		q = devm_kzalloc(dev, sizeof(qmem), GFP_KERNEL);
		if (!*q)
		return -ENOMEM;
		qmem = *q;

		qmem->entry_sz = entry_sz;
		qmem->alloc_sz = (qsize * entry_sz) + OTX2_ALIGN;
		qmem->base = dma_zalloc_coherent(dev, qmem->alloc_sz,
		&qmem->iova, GFP_KERNEL);
		if (!qmem->base)
		return -ENOMEM;

		qmem->qsize = qsize;

		aligned_addr = ALIGN((u64)qmem->iova, OTX2_ALIGN);
		qmem->align = (aligned_addr - qmem->iova);
		qmem->base += qmem->align;
		qmem->iova += qmem->align;
		return 0;
		}

		static inline void qmem_free(struct device dev, struct qmem qmem)
		{
		if (!qmem)
		return;

		if (qmem->base)
		dma_free_coherent(dev, qmem->alloc_sz,
		qmem->base - qmem->align,
		qmem->iova - qmem->align);
		devm_kfree(dev, qmem);
		}

		struct admin_queue {
		struct qmem *inst;
		struct qmem *res;
		spinlock_t lock; /* Serialize inst enqueue from PFs */
		};

		/* NPA aura count */
		enum npa_aura_sz {
		NPA_AURA_SZ_0,
		NPA_AURA_SZ_128,
		NPA_AURA_SZ_256,
		NPA_AURA_SZ_512,
		NPA_AURA_SZ_1K,
		NPA_AURA_SZ_2K,
		NPA_AURA_SZ_4K,
		NPA_AURA_SZ_8K,
		NPA_AURA_SZ_16K,
		NPA_AURA_SZ_32K,
		NPA_AURA_SZ_64K,
		NPA_AURA_SZ_128K,
		NPA_AURA_SZ_256K,
		NPA_AURA_SZ_512K,
		NPA_AURA_SZ_1M,
		NPA_AURA_SZ_MAX,
		};

		#define NPA_AURA_COUNT(x) (1ULL << ((x) + 6))

		/* NPA AQ result structure for init/read/write of aura HW contexts */
		struct npa_aq_aura_res {
		struct npa_aq_res_s res;
		struct npa_aura_s aura_ctx;
		struct npa_aura_s ctx_mask;
		};

		/* NPA AQ result structure for init/read/write of pool HW contexts */
		struct npa_aq_pool_res {
		struct npa_aq_res_s res;
		struct npa_pool_s pool_ctx;
		struct npa_pool_s ctx_mask;
		};

		/* NIX Transmit schedulers */
		enum nix_scheduler {
		NIX_TXSCH_LVL_SMQ = 0x0,
		NIX_TXSCH_LVL_MDQ = 0x0,
		NIX_TXSCH_LVL_TL4 = 0x1,
		NIX_TXSCH_LVL_TL3 = 0x2,
		NIX_TXSCH_LVL_TL2 = 0x3,
		NIX_TXSCH_LVL_TL1 = 0x4,
		NIX_TXSCH_LVL_CNT = 0x5,
		};

		/* NIX LSO format indices.
		* As of now TSO is the only one using, so statically assigning indices.
		*/
		#define NIX_LSO_FORMAT_IDX_TSOV4 0
		#define NIX_LSO_FORMAT_IDX_TSOV6 1

		/* RSS info */
		#define MAX_RSS_GROUPS 8
		/* Group 0 has to be used in default pkt forwarding MCAM entries
		* reserved for NIXLFs. Groups 1-7 can be used for RSS for ntuple
		* filters.
		*/
		#define DEFAULT_RSS_CONTEXT_GROUP 0
		#define MAX_RSS_INDIR_TBL_SIZE 256 /* 1 << Max adder bits */

		#endif /* COMMON_H */

drivers/net/ethernet/marvell/octeontx2/af/mbox.h

+206 −0

Original line number	Diff line number	Diff line
		@@ -124,21 +124,50 @@ M(ATTACH_RESOURCES, 0x002, rsrc_attach, msg_rsp) \
		M(DETACH_RESOURCES, 0x003, rsrc_detach, msg_rsp) \
		M(MSIX_OFFSET, 0x004, msg_req, msix_offset_rsp) \
		/* CGX mbox IDs (range 0x200 - 0x3FF) */ \
		M(CGX_START_RXTX, 0x200, msg_req, msg_rsp) \
		M(CGX_STOP_RXTX, 0x201, msg_req, msg_rsp) \
		M(CGX_STATS, 0x202, msg_req, cgx_stats_rsp) \
		M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set_or_get, \
		cgx_mac_addr_set_or_get) \
		M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_set_or_get, \
		cgx_mac_addr_set_or_get) \
		M(CGX_PROMISC_ENABLE, 0x205, msg_req, msg_rsp) \
		M(CGX_PROMISC_DISABLE, 0x206, msg_req, msg_rsp) \
		M(CGX_START_LINKEVENTS, 0x207, msg_req, msg_rsp) \
		M(CGX_STOP_LINKEVENTS, 0x208, msg_req, msg_rsp) \
		M(CGX_GET_LINKINFO, 0x209, msg_req, cgx_link_info_msg) \
		M(CGX_INTLBK_ENABLE, 0x20A, msg_req, msg_rsp) \
		M(CGX_INTLBK_DISABLE, 0x20B, msg_req, msg_rsp) \
		/* NPA mbox IDs (range 0x400 - 0x5FF) */ \
		M(NPA_LF_ALLOC, 0x400, npa_lf_alloc_req, npa_lf_alloc_rsp) \
		M(NPA_LF_FREE, 0x401, msg_req, msg_rsp) \
		M(NPA_AQ_ENQ, 0x402, npa_aq_enq_req, npa_aq_enq_rsp) \
		M(NPA_HWCTX_DISABLE, 0x403, hwctx_disable_req, msg_rsp) \
		/* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \
		/* TIM mbox IDs (range 0x800 - 0x9FF) */ \
		/* CPT mbox IDs (range 0xA00 - 0xBFF) */ \
		/* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \
		/* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \
		M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc_req, nix_lf_alloc_rsp) \
		M(NIX_LF_FREE, 0x8001, msg_req, msg_rsp) \
		M(NIX_AQ_ENQ, 0x8002, nix_aq_enq_req, nix_aq_enq_rsp) \
		M(NIX_HWCTX_DISABLE, 0x8003, hwctx_disable_req, msg_rsp)

		/* Messages initiated by AF (range 0xC00 - 0xDFF) */
		#define MBOX_UP_CGX_MESSAGES \
		M(CGX_LINK_EVENT, 0xC00, cgx_link_info_msg, msg_rsp)

		enum {
		#define M(_name, _id, _1, _2) MBOX_MSG_ ## _name = _id,
		MBOX_MESSAGES
		MBOX_UP_CGX_MESSAGES
		#undef M
		};

		/* Mailbox message formats */

		#define RVU_DEFAULT_PF_FUNC 0xFFFF

		/* Generic request msg used for those mbox messages which
		* don't send any data in the request.
		*/
		@@ -208,4 +237,181 @@ struct msix_offset_rsp {
		u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT];
		};

		/* CGX mbox message formats */

		struct cgx_stats_rsp {
		struct mbox_msghdr hdr;
		#define CGX_RX_STATS_COUNT 13
		#define CGX_TX_STATS_COUNT 18
		u64 rx_stats[CGX_RX_STATS_COUNT];
		u64 tx_stats[CGX_TX_STATS_COUNT];
		};

		/* Structure for requesting the operation for
		* setting/getting mac address in the CGX interface
		*/
		struct cgx_mac_addr_set_or_get {
		struct mbox_msghdr hdr;
		u8 mac_addr[ETH_ALEN];
		};

		struct cgx_link_user_info {
		uint64_t link_up:1;
		uint64_t full_duplex:1;
		uint64_t lmac_type_id:4;
		uint64_t speed:20; /* speed in Mbps */
		#define LMACTYPE_STR_LEN 16
		char lmac_type[LMACTYPE_STR_LEN];
		};

		struct cgx_link_info_msg {
		struct mbox_msghdr hdr;
		struct cgx_link_user_info link_info;
		};

		/* NPA mbox message formats */

		/* NPA mailbox error codes
		* Range 301 - 400.
		*/
		enum npa_af_status {
		NPA_AF_ERR_PARAM = -301,
		NPA_AF_ERR_AQ_FULL = -302,
		NPA_AF_ERR_AQ_ENQUEUE = -303,
		NPA_AF_ERR_AF_LF_INVALID = -304,
		NPA_AF_ERR_AF_LF_ALLOC = -305,
		NPA_AF_ERR_LF_RESET = -306,
		};

		/* For NPA LF context alloc and init */
		struct npa_lf_alloc_req {
		struct mbox_msghdr hdr;
		int node;
		int aura_sz; /* No of auras */
		u32 nr_pools; /* No of pools */
		};

		struct npa_lf_alloc_rsp {
		struct mbox_msghdr hdr;
		u32 stack_pg_ptrs; /* No of ptrs per stack page */
		u32 stack_pg_bytes; /* Size of stack page */
		u16 qints; /* NPA_AF_CONST::QINTS */
		};

		/* NPA AQ enqueue msg */
		struct npa_aq_enq_req {
		struct mbox_msghdr hdr;
		u32 aura_id;
		u8 ctype;
		u8 op;
		union {
		/* Valid when op == WRITE/INIT and ctype == AURA.
		* LF fills the pool_id in aura.pool_addr. AF will translate
		* the pool_id to pool context pointer.
		*/
		struct npa_aura_s aura;
		/* Valid when op == WRITE/INIT and ctype == POOL */
		struct npa_pool_s pool;
		};
		/* Mask data when op == WRITE (1=write, 0=don't write) */
		union {
		/* Valid when op == WRITE and ctype == AURA */
		struct npa_aura_s aura_mask;
		/* Valid when op == WRITE and ctype == POOL */
		struct npa_pool_s pool_mask;
		};
		};

		struct npa_aq_enq_rsp {
		struct mbox_msghdr hdr;
		union {
		/* Valid when op == READ and ctype == AURA */
		struct npa_aura_s aura;
		/* Valid when op == READ and ctype == POOL */
		struct npa_pool_s pool;
		};
		};

		/* Disable all contexts of type 'ctype' */
		struct hwctx_disable_req {
		struct mbox_msghdr hdr;
		u8 ctype;
		};

		/* NIX mailbox error codes
		* Range 401 - 500.
		*/
		enum nix_af_status {
		NIX_AF_ERR_PARAM = -401,
		NIX_AF_ERR_AQ_FULL = -402,
		NIX_AF_ERR_AQ_ENQUEUE = -403,
		NIX_AF_ERR_AF_LF_INVALID = -404,
		NIX_AF_ERR_AF_LF_ALLOC = -405,
		NIX_AF_ERR_TLX_ALLOC_FAIL = -406,
		NIX_AF_ERR_TLX_INVALID = -407,
		NIX_AF_ERR_RSS_SIZE_INVALID = -408,
		NIX_AF_ERR_RSS_GRPS_INVALID = -409,
		NIX_AF_ERR_FRS_INVALID = -410,
		NIX_AF_ERR_RX_LINK_INVALID = -411,
		NIX_AF_INVAL_TXSCHQ_CFG = -412,
		NIX_AF_SMQ_FLUSH_FAILED = -413,
		NIX_AF_ERR_LF_RESET = -414,
		};

		/* For NIX LF context alloc and init */
		struct nix_lf_alloc_req {
		struct mbox_msghdr hdr;
		int node;
		u32 rq_cnt; /* No of receive queues */
		u32 sq_cnt; /* No of send queues */
		u32 cq_cnt; /* No of completion queues */
		u8 xqe_sz;
		u16 rss_sz;
		u8 rss_grps;
		u16 npa_func;
		u16 sso_func;
		u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */
		};

		struct nix_lf_alloc_rsp {
		struct mbox_msghdr hdr;
		u16 sqb_size;
		u8 lso_tsov4_idx;
		u8 lso_tsov6_idx;
		u8 mac_addr[ETH_ALEN];
		};

		/* NIX AQ enqueue msg */
		struct nix_aq_enq_req {
		struct mbox_msghdr hdr;
		u32 qidx;
		u8 ctype;
		u8 op;
		union {
		struct nix_rq_ctx_s rq;
		struct nix_sq_ctx_s sq;
		struct nix_cq_ctx_s cq;
		struct nix_rsse_s rss;
		struct nix_rx_mce_s mce;
		};
		union {
		struct nix_rq_ctx_s rq_mask;
		struct nix_sq_ctx_s sq_mask;
		struct nix_cq_ctx_s cq_mask;
		struct nix_rsse_s rss_mask;
		struct nix_rx_mce_s mce_mask;
		};
		};

		struct nix_aq_enq_rsp {
		struct mbox_msghdr hdr;
		union {
		struct nix_rq_ctx_s rq;
		struct nix_sq_ctx_s sq;
		struct nix_cq_ctx_s cq;
		struct nix_rsse_s rss;
		struct nix_rx_mce_s mce;
		};
		};

		#endif /* MBOX_H */

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