Commit e8d992fb authored by Fabio Estevam's avatar Fabio Estevam Committed by Shawn Guo
Browse files

ARM: imx: Remove iomux-v3 board code 



IMX_HAVE_IOMUX_V3 was only used by i.MX25/35 board files. Since the
board files users are gone, it is safe to remove iomux-v3 related
code.

Signed-off-by: default avatarFabio Estevam <festevam@gmail.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 6c5f05a6

arch/arm/mach-imx/Kconfig

+0 −5
Original line number Diff line number Diff line
@@ -47,9 +47,6 @@ config HAVE_IMX_SRC 
	def_bool y if SMP

	select ARCH_HAS_RESET_CONTROLLER



config ARCH_MXC_IOMUX_V3

	bool



if ARCH_MULTI_V6



comment "ARM1136 platforms"
@@ -63,7 +60,6 @@ config SOC_IMX31 


config SOC_IMX35

	bool "i.MX35 support"

	select ARCH_MXC_IOMUX_V3

	select MXC_AVIC

	select PINCTRL_IMX35

	help
@@ -87,7 +83,6 @@ if ARCH_MULTI_V5 


config SOC_IMX25

	bool "i.MX25 support"

	select ARCH_MXC_IOMUX_V3

	select CPU_ARM926T

	select MXC_AVIC

	select PINCTRL_IMX25

arch/arm/mach-imx/Makefile

+0 −2
Original line number Diff line number Diff line
@@ -11,8 +11,6 @@ obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o mach-imx35.o 
imx5-pm-$(CONFIG_PM) += pm-imx5.o

obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o $(imx5-pm-y)



obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o



obj-$(CONFIG_MXC_TZIC) += tzic.o

obj-$(CONFIG_MXC_AVIC) += avic.o

arch/arm/mach-imx/iomux-v3.c

deleted100644 → 0
+0 −65
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-or-later

/*

 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.

 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>

 * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,

 *                       <armlinux@phytec.de>

 */

#include <linux/errno.h>

#include <linux/init.h>

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/string.h>

#include <linux/gpio.h>



#include <asm/mach/map.h>



#include "hardware.h"

#include "iomux-v3.h"



static void __iomem *base;



/*

 * configures a single pad in the iomuxer

 */

int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad)

{

	u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;

	u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;

	u32 sel_input_ofs = (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;

	u32 sel_input = (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;

	u32 pad_ctrl_ofs = (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;

	u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;



	if (mux_ctrl_ofs)

		imx_writel(mux_mode, base + mux_ctrl_ofs);



	if (sel_input_ofs)

		imx_writel(sel_input, base + sel_input_ofs);



	if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)

		imx_writel(pad_ctrl, base + pad_ctrl_ofs);



	return 0;

}



int mxc_iomux_v3_setup_multiple_pads(const iomux_v3_cfg_t *pad_list,

		unsigned count)

{

	const iomux_v3_cfg_t *p = pad_list;

	int i;

	int ret;



	for (i = 0; i < count; i++) {

		ret = mxc_iomux_v3_setup_pad(*p);

		if (ret)

			return ret;

		p++;

	}

	return 0;

}



void mxc_iomux_v3_init(void __iomem *iomux_v3_base)

{

	base = iomux_v3_base;

}

arch/arm/mach-imx/iomux-v3.h

deleted100644 → 0
+0 −130
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-or-later */

/*

 * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,

 *			<armlinux@phytec.de>

 */



#ifndef __MACH_IOMUX_V3_H__

#define __MACH_IOMUX_V3_H__



/*

 *	build IOMUX_PAD structure

 *

 * This iomux scheme is based around pads, which are the physical balls

 * on the processor.

 *

 * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls

 *   things like driving strength and pullup/pulldown.

 * - Each pad can have but not necessarily does have an output routing register

 *   (IOMUXC_SW_MUX_CTL_PAD_x).

 * - Each pad can have but not necessarily does have an input routing register

 *   (IOMUXC_x_SELECT_INPUT)

 *

 * The three register sets do not have a fixed offset to each other,

 * hence we order this table by pad control registers (which all pads

 * have) and put the optional i/o routing registers into additional

 * fields.

 *

 * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode>

 * If <padname> or <padmode> refers to a GPIO, it is named

 * GPIO_<unit>_<num>

 *

 * IOMUX/PAD Bit field definitions

 *

 * MUX_CTRL_OFS:	    0..11 (12)

 * PAD_CTRL_OFS:	   12..23 (12)

 * SEL_INPUT_OFS:	   24..35 (12)

 * MUX_MODE + SION:	   36..40  (5)

 * PAD_CTRL + NO_PAD_CTRL: 41..57 (17)

 * SEL_INP:		   58..61  (4)

 * reserved:		     63    (1)

*/



typedef u64 iomux_v3_cfg_t;



#define MUX_CTRL_OFS_SHIFT	0

#define MUX_CTRL_OFS_MASK	((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)

#define MUX_PAD_CTRL_OFS_SHIFT	12

#define MUX_PAD_CTRL_OFS_MASK	((iomux_v3_cfg_t)0xfff << MUX_PAD_CTRL_OFS_SHIFT)

#define MUX_SEL_INPUT_OFS_SHIFT	24

#define MUX_SEL_INPUT_OFS_MASK	((iomux_v3_cfg_t)0xfff << MUX_SEL_INPUT_OFS_SHIFT)



#define MUX_MODE_SHIFT		36

#define MUX_MODE_MASK		((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)

#define MUX_PAD_CTRL_SHIFT	41

#define MUX_PAD_CTRL_MASK	((iomux_v3_cfg_t)0x1ffff << MUX_PAD_CTRL_SHIFT)

#define MUX_SEL_INPUT_SHIFT	58

#define MUX_SEL_INPUT_MASK	((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)



#define MUX_PAD_CTRL(x)		((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)



#define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _sel_input_ofs, \

		_sel_input, _pad_ctrl)					\

	(((iomux_v3_cfg_t)(_mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) |	\

		((iomux_v3_cfg_t)(_mux_mode) << MUX_MODE_SHIFT) |	\

		((iomux_v3_cfg_t)(_pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \

		((iomux_v3_cfg_t)(_pad_ctrl) << MUX_PAD_CTRL_SHIFT) |	\

		((iomux_v3_cfg_t)(_sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT) | \

		((iomux_v3_cfg_t)(_sel_input) << MUX_SEL_INPUT_SHIFT))



#define NEW_PAD_CTRL(cfg, pad)	(((cfg) & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(pad))

/*

 * Use to set PAD control

 */



#define NO_PAD_CTRL			(1 << 16)

#define PAD_CTL_DVS			(1 << 13)

#define PAD_CTL_HYS			(1 << 8)



#define PAD_CTL_PKE			(1 << 7)

#define PAD_CTL_PUE			(1 << 6 | PAD_CTL_PKE)

#define PAD_CTL_PUS_100K_DOWN		(0 << 4 | PAD_CTL_PUE)

#define PAD_CTL_PUS_47K_UP		(1 << 4 | PAD_CTL_PUE)

#define PAD_CTL_PUS_100K_UP		(2 << 4 | PAD_CTL_PUE)

#define PAD_CTL_PUS_22K_UP		(3 << 4 | PAD_CTL_PUE)



#define PAD_CTL_ODE			(1 << 3)



#define PAD_CTL_DSE_LOW			(0 << 1)

#define PAD_CTL_DSE_MED			(1 << 1)

#define PAD_CTL_DSE_HIGH		(2 << 1)

#define PAD_CTL_DSE_MAX			(3 << 1)



#define PAD_CTL_SRE_FAST		(1 << 0)

#define PAD_CTL_SRE_SLOW		(0 << 0)



#define IOMUX_CONFIG_SION		(0x1 << 4)



#define MX51_NUM_GPIO_PORT	4



#define GPIO_PIN_MASK 0x1f



#define GPIO_PORT_SHIFT 5

#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)



#define GPIO_PORTA	(0 << GPIO_PORT_SHIFT)

#define GPIO_PORTB	(1 << GPIO_PORT_SHIFT)

#define GPIO_PORTC	(2 << GPIO_PORT_SHIFT)

#define GPIO_PORTD	(3 << GPIO_PORT_SHIFT)

#define GPIO_PORTE	(4 << GPIO_PORT_SHIFT)

#define GPIO_PORTF	(5 << GPIO_PORT_SHIFT)



/*

 * setups a single pad in the iomuxer

 */

int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad);



/*

 * setups multiple pads

 * convenient way to call the above function with tables

 */

int mxc_iomux_v3_setup_multiple_pads(const iomux_v3_cfg_t *pad_list,

		unsigned count);



/*

 * Initialise the iomux controller

 */

void mxc_iomux_v3_init(void __iomem *iomux_v3_base);



#endif /* __MACH_IOMUX_V3_H__*/

arch/arm/mach-imx/mm-imx3.c

+0 −2
Original line number Diff line number Diff line
@@ -21,7 +21,6 @@ 
#include "crmregs-imx3.h"

#include "devices/devices-common.h"

#include "hardware.h"

#include "iomux-v3.h"



void __iomem *mx3_ccm_base;
@@ -140,7 +139,6 @@ static void imx35_idle(void) 
void __init imx35_init_early(void)

{

	mxc_set_cpu_type(MXC_CPU_MX35);

	mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));

	arm_pm_idle = imx35_idle;

	arch_ioremap_caller = imx3_ioremap_caller;

	mx3_ccm_base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR);

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