Commit e8c9d35e authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'tegra-for-5.10-soc' of... 

Merge tag 'tegra-for-5.10-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers

soc/tegra: Changes for v5.10-rc1

These changes contain a bit of cleanup and chip support for the upcoming
Tegra234 SoC.

* tag 'tegra-for-5.10-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  soc/tegra: pmc: Add Tegra234 support
  soc/tegra: pmc: Reorder reset sources/levels definitions
  soc/tegra: misc: Add Tegra234 support
  soc/tegra: fuse: Add Tegra234 support
  soc/tegra: fuse: Implement tegra_is_silicon()
  soc/tegra: fuse: Extract tegra_get_platform()

Link: https://lore.kernel.org/r/20200918150303.3938852-2-thierry.reding@gmail.com


Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 5746b3b8 34e214a9

drivers/soc/tegra/fuse/fuse-tegra.c

+6 −2
Original line number Diff line number Diff line
@@ -49,6 +49,9 @@ static struct tegra_fuse *fuse = &(struct tegra_fuse) { 
};



static const struct of_device_id tegra_fuse_match[] = {

#ifdef CONFIG_ARCH_TEGRA_234_SOC

	{ .compatible = "nvidia,tegra234-efuse", .data = &tegra234_fuse_soc },

#endif

#ifdef CONFIG_ARCH_TEGRA_194_SOC

	{ .compatible = "nvidia,tegra194-efuse", .data = &tegra194_fuse_soc },

#endif
@@ -326,7 +329,8 @@ const struct attribute_group tegra_soc_attr_group = { 
	.attrs = tegra_soc_attr,

};



#ifdef CONFIG_ARCH_TEGRA_194_SOC

#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \

    IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC)

static ssize_t platform_show(struct device *dev, struct device_attribute *attr,

			     char *buf)

{
@@ -336,7 +340,7 @@ static ssize_t platform_show(struct device *dev, struct device_attribute *attr, 
	 * platform type is silicon and all other non-zero values indicate

	 * the type of simulation platform is being used.

	 */

	return sprintf(buf, "%d\n", (tegra_read_chipid() >> 20) & 0xf);

	return sprintf(buf, "%d\n", tegra_get_platform());

}



static DEVICE_ATTR_RO(platform);

drivers/soc/tegra/fuse/fuse-tegra30.c

+30 −0
Original line number Diff line number Diff line
@@ -356,3 +356,33 @@ const struct tegra_fuse_soc tegra194_fuse_soc = { 
	.soc_attr_group = &tegra194_soc_attr_group,

};

#endif



#if defined(CONFIG_ARCH_TEGRA_234_SOC)

static const struct nvmem_cell_lookup tegra234_fuse_lookups[] = {

	{

		.nvmem_name = "fuse",

		.cell_name = "xusb-pad-calibration",

		.dev_id = "3520000.padctl",

		.con_id = "calibration",

	}, {

		.nvmem_name = "fuse",

		.cell_name = "xusb-pad-calibration-ext",

		.dev_id = "3520000.padctl",

		.con_id = "calibration-ext",

	},

};



static const struct tegra_fuse_info tegra234_fuse_info = {

	.read = tegra30_fuse_read,

	.size = 0x300,

	.spare = 0x280,

};



const struct tegra_fuse_soc tegra234_fuse_soc = {

	.init = tegra30_fuse_init,

	.info = &tegra234_fuse_info,

	.lookups = tegra234_fuse_lookups,

	.num_lookups = ARRAY_SIZE(tegra234_fuse_lookups),

	.soc_attr_group = &tegra194_soc_attr_group,

};

#endif

drivers/soc/tegra/fuse/fuse.h

+9 −1
Original line number Diff line number Diff line
@@ -115,9 +115,17 @@ extern const struct tegra_fuse_soc tegra210_fuse_soc; 
extern const struct tegra_fuse_soc tegra186_fuse_soc;

#endif



#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \

    IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC)

extern const struct attribute_group tegra194_soc_attr_group;

#endif



#ifdef CONFIG_ARCH_TEGRA_194_SOC

extern const struct tegra_fuse_soc tegra194_fuse_soc;

extern const struct attribute_group tegra194_soc_attr_group;

#endif



#ifdef CONFIG_ARCH_TEGRA_234_SOC

extern const struct tegra_fuse_soc tegra234_fuse_soc;

#endif



#endif

drivers/soc/tegra/fuse/tegra-apbmisc.c

+26 −0
Original line number Diff line number Diff line
@@ -47,6 +47,31 @@ u8 tegra_get_minor_rev(void) 
	return (tegra_read_chipid() >> 16) & 0xf;

}



u8 tegra_get_platform(void)

{

	return (tegra_read_chipid() >> 20) & 0xf;

}



bool tegra_is_silicon(void)

{

	switch (tegra_get_chip_id()) {

	case TEGRA194:

	case TEGRA234:

		if (tegra_get_platform() == 0)

			return true;



		return false;

	}



	/*

	 * Chips prior to Tegra194 have a different way of determining whether

	 * they are silicon or not. Since we never supported simulation on the

	 * older Tegra chips, don't bother extracting the information and just

	 * report that we're running on silicon.

	 */

	return true;

}



u32 tegra_read_straps(void)

{

	WARN(!chipid, "Tegra ABP MISC not yet available\n");
@@ -70,6 +95,7 @@ static const struct of_device_id apbmisc_match[] __initconst = { 
	{ .compatible = "nvidia,tegra20-apbmisc", },

	{ .compatible = "nvidia,tegra186-misc", },

	{ .compatible = "nvidia,tegra194-misc", },

	{ .compatible = "nvidia,tegra234-misc", },

	{},

};

drivers/soc/tegra/pmc.c

+107 −39
Original line number Diff line number Diff line
@@ -336,45 +336,6 @@ struct tegra_pmc_soc { 
	bool has_blink_output;

};



static const char * const tegra186_reset_sources[] = {

	"SYS_RESET",

	"AOWDT",

	"MCCPLEXWDT",

	"BPMPWDT",

	"SCEWDT",

	"SPEWDT",

	"APEWDT",

	"BCCPLEXWDT",

	"SENSOR",

	"AOTAG",

	"VFSENSOR",

	"SWREST",

	"SC7",

	"HSM",

	"CORESIGHT"

};



static const char * const tegra186_reset_levels[] = {

	"L0", "L1", "L2", "WARM"

};



static const char * const tegra30_reset_sources[] = {

	"POWER_ON_RESET",

	"WATCHDOG",

	"SENSOR",

	"SW_MAIN",

	"LP0"

};



static const char * const tegra210_reset_sources[] = {

	"POWER_ON_RESET",

	"WATCHDOG",

	"SENSOR",

	"SW_MAIN",

	"LP0",

	"AOTAG"

};



/**

 * struct tegra_pmc - NVIDIA Tegra PMC

 * @dev: pointer to PMC device structure
@@ -2784,6 +2745,14 @@ static const u8 tegra30_cpu_powergates[] = { 
	TEGRA_POWERGATE_CPU3,

};



static const char * const tegra30_reset_sources[] = {

	"POWER_ON_RESET",

	"WATCHDOG",

	"SENSOR",

	"SW_MAIN",

	"LP0"

};



static const struct tegra_pmc_soc tegra30_pmc_soc = {

	.num_powergates = ARRAY_SIZE(tegra30_powergates),

	.powergates = tegra30_powergates,
@@ -3061,6 +3030,15 @@ static const struct pinctrl_pin_desc tegra210_pin_descs[] = { 
	TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)

};



static const char * const tegra210_reset_sources[] = {

	"POWER_ON_RESET",

	"WATCHDOG",

	"SENSOR",

	"SW_MAIN",

	"LP0",

	"AOTAG"

};



static const struct tegra_wake_event tegra210_wake_events[] = {

	TEGRA_WAKE_IRQ("rtc", 16, 2),

	TEGRA_WAKE_IRQ("pmu", 51, 86),
@@ -3193,6 +3171,28 @@ static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 
	iounmap(wake);

}



static const char * const tegra186_reset_sources[] = {

	"SYS_RESET",

	"AOWDT",

	"MCCPLEXWDT",

	"BPMPWDT",

	"SCEWDT",

	"SPEWDT",

	"APEWDT",

	"BCCPLEXWDT",

	"SENSOR",

	"AOTAG",

	"VFSENSOR",

	"SWREST",

	"SC7",

	"HSM",

	"CORESIGHT"

};



static const char * const tegra186_reset_levels[] = {

	"L0", "L1", "L2", "WARM"

};



static const struct tegra_wake_event tegra186_wake_events[] = {

	TEGRA_WAKE_IRQ("pmu", 24, 209),

	TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)),
@@ -3362,7 +3362,75 @@ static const struct tegra_pmc_soc tegra194_pmc_soc = { 
	.has_blink_output = false,

};



static const struct tegra_pmc_regs tegra234_pmc_regs = {

	.scratch0 = 0x2000,

	.dpd_req = 0,

	.dpd_status = 0,

	.dpd2_req = 0,

	.dpd2_status = 0,

	.rst_status = 0x70,

	.rst_source_shift = 0x2,

	.rst_source_mask = 0xfc,

	.rst_level_shift = 0x0,

	.rst_level_mask = 0x3,

};



static const char * const tegra234_reset_sources[] = {

	"SYS_RESET_N",

	"AOWDT",

	"BCCPLEXWDT",

	"BPMPWDT",

	"SCEWDT",

	"SPEWDT",

	"APEWDT",

	"LCCPLEXWDT",

	"SENSOR",

	"AOTAG",

	"VFSENSOR",

	"MAINSWRST",

	"SC7",

	"HSM",

	"CSITE",

	"RCEWDT",

	"PVA0WDT",

	"PVA1WDT",

	"L1A_ASYNC",

	"BPMPBOOT",

	"FUSECRC",

};



static const struct tegra_pmc_soc tegra234_pmc_soc = {

	.num_powergates = 0,

	.powergates = NULL,

	.num_cpu_powergates = 0,

	.cpu_powergates = NULL,

	.has_tsense_reset = false,

	.has_gpu_clamps = false,

	.needs_mbist_war = false,

	.has_impl_33v_pwr = true,

	.maybe_tz_only = false,

	.num_io_pads = 0,

	.io_pads = NULL,

	.num_pin_descs = 0,

	.pin_descs = NULL,

	.regs = &tegra234_pmc_regs,

	.init = NULL,

	.setup_irq_polarity = tegra186_pmc_setup_irq_polarity,

	.irq_set_wake = tegra186_pmc_irq_set_wake,

	.irq_set_type = tegra186_pmc_irq_set_type,

	.reset_sources = tegra234_reset_sources,

	.num_reset_sources = ARRAY_SIZE(tegra234_reset_sources),

	.reset_levels = tegra186_reset_levels,

	.num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),

	.num_wake_events = 0,

	.wake_events = NULL,

	.pmc_clks_data = NULL,

	.num_pmc_clks = 0,

	.has_blink_output = false,

};



static const struct of_device_id tegra_pmc_match[] = {

	{ .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc },

	{ .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },

	{ .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },

	{ .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },

CRA Git | Maintained and supported by SUSTech CRA and CCSE