Commit e8adb3a0 authored Aug 30, 2019 by Geert Uytterhoeven

clk: renesas: rcar-gen3: Avoid double table iteration in SD .set_rate()



The .set_rate() callback for the SD clocks is always called with a valid
clock rate, returned by .round_rate().  Hence there is no need to
iterate through the divider table twice: once to repeat the work done by
.round_rate(), and a second time to find the corresponding divider
entry.

Just iterate once, looking for the divider that matches the passed clock
rate.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20190830134515.11925-4-geert+renesas@glider.be

parent b5dea62d

drivers/clk/renesas/rcar-gen3-cpg.c

+3 −3

Original line number	Diff line number	Diff line
		@@ -342,11 +342,11 @@ static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
		{
		struct sd_clock *clock = to_sd_clock(hw);
		unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate);
		unsigned int i;

		for (i = 0; i < clock->div_num; i++)
		if (div == clock->div_table[i].div)
		if (rate == DIV_ROUND_CLOSEST(parent_rate,
		clock->div_table[i].div))
		break;

		if (i >= clock->div_num)

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