Commit e8a8d867 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch '40GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue 



Jeff Kirsher says:

====================
40GbE Intel Wired LAN Driver Updates 2017-10-31

This series contains updates to i40e, i40evf and net/sched.

Arnd Bergmann cleans up the power management code to resolve a build
warning.

Shannon Nelson fixes i40e to only redistribute our vectors when we did
not get the full count that we requested.

Alex reverts a previous commit because it potentially causes a memory leak
when combined with the current page recycling scheme.

Amritha enables configuring cloud filters in i40e using the tc-flower
classifier.  The classification function of the filter is to match a
packet to a traffic class.  cls_flower is extended to offload classid to
hardware.  Hardware traffic classes are identified using classid values
reserved in the range :ffe0 - :ffef.
The cloud filters are added for a VSI and are cleaned up when the VSI is
deleted. The filters that match on L4 ports needs enhanced admin queue
functions with big buffer support for extended fields in cloud filter
commands.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 170b8ffa 2f4b411a

drivers/net/ethernet/intel/i40e/i40e.h

+62 −0
Original line number Original line Diff line number Diff line
@@ -55,6 +55,8 @@ 
#include <linux/net_tstamp.h>

#include <linux/net_tstamp.h>

#include <linux/ptp_clock_kernel.h>

#include <linux/ptp_clock_kernel.h>

#include <net/pkt_cls.h>

#include <net/pkt_cls.h>

#include <net/tc_act/tc_gact.h>

#include <net/tc_act/tc_mirred.h>

#include "i40e_type.h"

#include "i40e_type.h"

#include "i40e_prototype.h"

#include "i40e_prototype.h"

#include "i40e_client.h"

#include "i40e_client.h"
@@ -253,6 +255,58 @@ struct i40e_fdir_filter { 
	u32 fd_id;

	u32 fd_id;

};

};





#define I40E_CLOUD_FIELD_OMAC	0x01

#define I40E_CLOUD_FIELD_IMAC	0x02

#define I40E_CLOUD_FIELD_IVLAN	0x04

#define I40E_CLOUD_FIELD_TEN_ID	0x08

#define I40E_CLOUD_FIELD_IIP	0x10



#define I40E_CLOUD_FILTER_FLAGS_OMAC	I40E_CLOUD_FIELD_OMAC

#define I40E_CLOUD_FILTER_FLAGS_IMAC	I40E_CLOUD_FIELD_IMAC

#define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN	(I40E_CLOUD_FIELD_IMAC | \

						 I40E_CLOUD_FIELD_IVLAN)

#define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID	(I40E_CLOUD_FIELD_IMAC | \

						 I40E_CLOUD_FIELD_TEN_ID)

#define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \

						  I40E_CLOUD_FIELD_IMAC | \

						  I40E_CLOUD_FIELD_TEN_ID)

#define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \

						   I40E_CLOUD_FIELD_IVLAN | \

						   I40E_CLOUD_FIELD_TEN_ID)

#define I40E_CLOUD_FILTER_FLAGS_IIP	I40E_CLOUD_FIELD_IIP



struct i40e_cloud_filter {

	struct hlist_node cloud_node;

	unsigned long cookie;

	/* cloud filter input set follows */

	u8 dst_mac[ETH_ALEN];

	u8 src_mac[ETH_ALEN];

	__be16 vlan_id;

	u16 seid;       /* filter control */

	__be16 dst_port;

	__be16 src_port;

	u32 tenant_id;

	union {

		struct {

			struct in_addr dst_ip;

			struct in_addr src_ip;

		} v4;

		struct {

			struct in6_addr dst_ip6;

			struct in6_addr src_ip6;

		} v6;

	} ip;

#define dst_ipv6	ip.v6.dst_ip6.s6_addr32

#define src_ipv6	ip.v6.src_ip6.s6_addr32

#define dst_ipv4	ip.v4.dst_ip.s_addr

#define src_ipv4	ip.v4.src_ip.s_addr

	u16 n_proto;    /* Ethernet Protocol */

	u8 ip_proto;    /* IPPROTO value */

	u8 flags;

#define I40E_CLOUD_TNL_TYPE_NONE        0xff

	u8 tunnel_type;

};



#define I40E_ETH_P_LLDP			0x88cc

#define I40E_ETH_P_LLDP			0x88cc





#define I40E_DCB_PRIO_TYPE_STRICT	0

#define I40E_DCB_PRIO_TYPE_STRICT	0
@@ -420,6 +474,9 @@ struct i40e_pf { 
	struct i40e_udp_port_config udp_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];

	struct i40e_udp_port_config udp_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];

	u16 pending_udp_bitmap;

	u16 pending_udp_bitmap;





	struct hlist_head cloud_filter_list;

	u16 num_cloud_filters;



	enum i40e_interrupt_policy int_policy;

	enum i40e_interrupt_policy int_policy;

	u16 rx_itr_default;

	u16 rx_itr_default;

	u16 tx_itr_default;

	u16 tx_itr_default;
@@ -483,6 +540,8 @@ struct i40e_pf { 
#define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED	BIT(27)

#define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED	BIT(27)

#define I40E_FLAG_SOURCE_PRUNING_DISABLED	BIT(28)

#define I40E_FLAG_SOURCE_PRUNING_DISABLED	BIT(28)

#define I40E_FLAG_TC_MQPRIO			BIT(29)

#define I40E_FLAG_TC_MQPRIO			BIT(29)

#define I40E_FLAG_FD_SB_INACTIVE		BIT(30)

#define I40E_FLAG_FD_SB_TO_CLOUD_FILTER		BIT(31)





	struct i40e_client_instance *cinst;

	struct i40e_client_instance *cinst;

	bool stat_offsets_loaded;

	bool stat_offsets_loaded;
@@ -565,6 +624,8 @@ struct i40e_pf { 
	u16 phy_led_val;

	u16 phy_led_val;





	u16 override_q_count;

	u16 override_q_count;

	u16 last_sw_conf_flags;

	u16 last_sw_conf_valid_flags;

};

};





/**

/**
@@ -739,6 +800,7 @@ struct i40e_vsi { 
	u16 next_base_queue;	/* next queue to be used for channel setup */

	u16 next_base_queue;	/* next queue to be used for channel setup */





	struct list_head ch_list;

	struct list_head ch_list;

	u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS];





	void *priv;	/* client driver data reference. */

	void *priv;	/* client driver data reference. */

drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h

+137 −3
Original line number Original line Diff line number Diff line
@@ -790,7 +790,35 @@ struct i40e_aqc_set_switch_config { 
	 */

	 */

	__le16	first_tag;

	__le16	first_tag;

	__le16	second_tag;

	__le16	second_tag;

	u8	reserved[6];

	/* Next byte is split into following:

	 * Bit 7    : 0 : No action, 1: Switch to mode defined by bits 6:0

	 * Bit 6    : 0 : Destination Port, 1: source port

	 * Bit 5..4 : L4 type

	 * 0: rsvd

	 * 1: TCP

	 * 2: UDP

	 * 3: Both TCP and UDP

	 * Bits 3:0 Mode

	 * 0: default mode

	 * 1: L4 port only mode

	 * 2: non-tunneled mode

	 * 3: tunneled mode

	 */

#define I40E_AQ_SET_SWITCH_BIT7_VALID		0x80



#define I40E_AQ_SET_SWITCH_L4_SRC_PORT		0x40



#define I40E_AQ_SET_SWITCH_L4_TYPE_RSVD		0x00

#define I40E_AQ_SET_SWITCH_L4_TYPE_TCP		0x10

#define I40E_AQ_SET_SWITCH_L4_TYPE_UDP		0x20

#define I40E_AQ_SET_SWITCH_L4_TYPE_BOTH		0x30



#define I40E_AQ_SET_SWITCH_MODE_DEFAULT		0x00

#define I40E_AQ_SET_SWITCH_MODE_L4_PORT		0x01

#define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL	0x02

#define I40E_AQ_SET_SWITCH_MODE_TUNNEL		0x03

	u8	mode;

	u8	rsvd5[5];

};

};





I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);

I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
@@ -1343,14 +1371,16 @@ struct i40e_aqc_add_remove_cloud_filters { 
#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT	0

#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT	0

#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK	(0x3FF << \

#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK	(0x3FF << \

					I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)

					I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)

	u8	reserved2[4];

	u8	big_buffer_flag;

#define I40E_AQC_ADD_CLOUD_CMD_BB	1

	u8	reserved2[3];

	__le32	addr_high;

	__le32	addr_high;

	__le32	addr_low;

	__le32	addr_low;

};

};





I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);

I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);





struct i40e_aqc_add_remove_cloud_filters_element_data {

struct i40e_aqc_cloud_filters_element_data {

	u8	outer_mac[6];

	u8	outer_mac[6];

	u8	inner_mac[6];

	u8	inner_mac[6];

	__le16	inner_vlan;

	__le16	inner_vlan;
@@ -1362,6 +1392,9 @@ struct i40e_aqc_add_remove_cloud_filters_element_data { 
		struct {

		struct {

			u8 data[16];

			u8 data[16];

		} v6;

		} v6;

		struct {

			__le16 data[8];

		} raw_v6;

	} ipaddr;

	} ipaddr;

	__le16	flags;

	__le16	flags;

#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT			0

#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT			0
@@ -1380,6 +1413,10 @@ struct i40e_aqc_add_remove_cloud_filters_element_data { 
#define I40E_AQC_ADD_CLOUD_FILTER_IMAC			0x000A

#define I40E_AQC_ADD_CLOUD_FILTER_IMAC			0x000A

#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC	0x000B

#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC	0x000B

#define I40E_AQC_ADD_CLOUD_FILTER_IIP			0x000C

#define I40E_AQC_ADD_CLOUD_FILTER_IIP			0x000C

/* 0x0010 to 0x0017 is for custom filters */

#define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT		0x0010 /* Dest IP + L4 Port */

#define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT		0x0011 /* Dest MAC + L4 Port */

#define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT		0x0012 /* Dest MAC + VLAN + L4 Port */





#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE		0x0080

#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE		0x0080

#define I40E_AQC_ADD_CLOUD_VNK_SHIFT			6

#define I40E_AQC_ADD_CLOUD_VNK_SHIFT			6
@@ -1414,6 +1451,49 @@ struct i40e_aqc_add_remove_cloud_filters_element_data { 
	u8	response_reserved[7];

	u8	response_reserved[7];

};

};





I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data);



/* i40e_aqc_cloud_filters_element_bb is used when

 * I40E_AQC_CLOUD_CMD_BB flag is set.

 */

struct i40e_aqc_cloud_filters_element_bb {

	struct i40e_aqc_cloud_filters_element_data element;

	u16     general_fields[32];

#define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0	0

#define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1	1

#define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2	2

#define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0	3

#define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1	4

#define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2	5

#define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0	6

#define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1	7

#define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2	8

#define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0	9

#define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1	10

#define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2	11

#define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0	12

#define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1	13

#define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2	14

#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0	15

#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1	16

#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2	17

#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3	18

#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4	19

#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5	20

#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6	21

#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7	22

#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0	23

#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1	24

#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2	25

#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3	26

#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4	27

#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5	28

#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6	29

#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7	30

};



I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb);



struct i40e_aqc_remove_cloud_filters_completion {

struct i40e_aqc_remove_cloud_filters_completion {

	__le16 perfect_ovlan_used;

	__le16 perfect_ovlan_used;

	__le16 perfect_ovlan_free;

	__le16 perfect_ovlan_free;
@@ -1425,6 +1505,60 @@ struct i40e_aqc_remove_cloud_filters_completion { 




I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);

I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);





/* Replace filter Command 0x025F

 * uses the i40e_aqc_replace_cloud_filters,

 * and the generic indirect completion structure

 */

struct i40e_filter_data {

	u8 filter_type;

	u8 input[3];

};



I40E_CHECK_STRUCT_LEN(4, i40e_filter_data);



struct i40e_aqc_replace_cloud_filters_cmd {

	u8      valid_flags;

#define I40E_AQC_REPLACE_L1_FILTER		0x0

#define I40E_AQC_REPLACE_CLOUD_FILTER		0x1

#define I40E_AQC_GET_CLOUD_FILTERS		0x2

#define I40E_AQC_MIRROR_CLOUD_FILTER		0x4

#define I40E_AQC_HIGH_PRIORITY_CLOUD_FILTER	0x8

	u8      old_filter_type;

	u8      new_filter_type;

	u8      tr_bit;

	u8      reserved[4];

	__le32 addr_high;

	__le32 addr_low;

};



I40E_CHECK_CMD_LENGTH(i40e_aqc_replace_cloud_filters_cmd);



struct i40e_aqc_replace_cloud_filters_cmd_buf {

	u8      data[32];

/* Filter type INPUT codes*/

#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX	3

#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED	BIT(7)



/* Field Vector offsets */

#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA	0

#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH	6

#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG	7

#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN	8

#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN	9

#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN	10

#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY	11

#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC	12

/* big FLU */

#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA	14

/* big FLU */

#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA	15



#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN	37

	struct i40e_filter_data filters[8];

};



I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf);



/* Add Mirror Rule (indirect or direct 0x0260)

/* Add Mirror Rule (indirect or direct 0x0260)

 * Delete Mirror Rule (indirect or direct 0x0261)

 * Delete Mirror Rule (indirect or direct 0x0261)

 * note: some rule types (4,5) do not use an external buffer.

 * note: some rule types (4,5) do not use an external buffer.

drivers/net/ethernet/intel/i40e/i40e_common.c

+192 −1
Original line number Original line Diff line number Diff line
@@ -2407,13 +2407,14 @@ i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw, 
 * @hw: pointer to the hardware structure

 * @hw: pointer to the hardware structure

 * @flags: bit flag values to set

 * @flags: bit flag values to set

 * @valid_flags: which bit flags to set

 * @valid_flags: which bit flags to set

 * @mode: cloud filter mode

 * @cmd_details: pointer to command details structure or NULL

 * @cmd_details: pointer to command details structure or NULL

 *

 *

 * Set switch configuration bits

 * Set switch configuration bits

 **/

 **/

enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,

enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,

						u16 flags,

						u16 flags,

						u16 valid_flags,

						u16 valid_flags, u8 mode,

				struct i40e_asq_cmd_details *cmd_details)

				struct i40e_asq_cmd_details *cmd_details)

{

{

	struct i40e_aq_desc desc;

	struct i40e_aq_desc desc;
@@ -2425,6 +2426,7 @@ enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw, 
					  i40e_aqc_opc_set_switch_config);

					  i40e_aqc_opc_set_switch_config);

	scfg->flags = cpu_to_le16(flags);

	scfg->flags = cpu_to_le16(flags);

	scfg->valid_flags = cpu_to_le16(valid_flags);

	scfg->valid_flags = cpu_to_le16(valid_flags);

	scfg->mode = mode;

	if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {

	if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {

		scfg->switch_tag = cpu_to_le16(hw->switch_tag);

		scfg->switch_tag = cpu_to_le16(hw->switch_tag);

		scfg->first_tag = cpu_to_le16(hw->first_tag);

		scfg->first_tag = cpu_to_le16(hw->first_tag);
@@ -5434,5 +5436,194 @@ i40e_add_pinfo_to_list(struct i40e_hw *hw, 




	status = i40e_aq_write_ppp(hw, (void *)sec, sec->data_end,

	status = i40e_aq_write_ppp(hw, (void *)sec, sec->data_end,

				   track_id, &offset, &info, NULL);

				   track_id, &offset, &info, NULL);



	return status;

}



/**

 * i40e_aq_add_cloud_filters

 * @hw: pointer to the hardware structure

 * @seid: VSI seid to add cloud filters from

 * @filters: Buffer which contains the filters to be added

 * @filter_count: number of filters contained in the buffer

 *

 * Set the cloud filters for a given VSI.  The contents of the

 * i40e_aqc_cloud_filters_element_data are filled in by the caller

 * of the function.

 *

 **/

enum i40e_status_code

i40e_aq_add_cloud_filters(struct i40e_hw *hw, u16 seid,

			  struct i40e_aqc_cloud_filters_element_data *filters,

			  u8 filter_count)

{

	struct i40e_aq_desc desc;

	struct i40e_aqc_add_remove_cloud_filters *cmd =

	(struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;

	enum i40e_status_code status;

	u16 buff_len;



	i40e_fill_default_direct_cmd_desc(&desc,

					  i40e_aqc_opc_add_cloud_filters);



	buff_len = filter_count * sizeof(*filters);

	desc.datalen = cpu_to_le16(buff_len);

	desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));

	cmd->num_filters = filter_count;

	cmd->seid = cpu_to_le16(seid);



	status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);



	return status;

}



/**

 * i40e_aq_add_cloud_filters_bb

 * @hw: pointer to the hardware structure

 * @seid: VSI seid to add cloud filters from

 * @filters: Buffer which contains the filters in big buffer to be added

 * @filter_count: number of filters contained in the buffer

 *

 * Set the big buffer cloud filters for a given VSI.  The contents of the

 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the

 * function.

 *

 **/

i40e_status

i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,

			     struct i40e_aqc_cloud_filters_element_bb *filters,

			     u8 filter_count)

{

	struct i40e_aq_desc desc;

	struct i40e_aqc_add_remove_cloud_filters *cmd =

	(struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;

	i40e_status status;

	u16 buff_len;

	int i;



	i40e_fill_default_direct_cmd_desc(&desc,

					  i40e_aqc_opc_add_cloud_filters);



	buff_len = filter_count * sizeof(*filters);

	desc.datalen = cpu_to_le16(buff_len);

	desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));

	cmd->num_filters = filter_count;

	cmd->seid = cpu_to_le16(seid);

	cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;



	for (i = 0; i < filter_count; i++) {

		u16 tnl_type;

		u32 ti;



		tnl_type = (le16_to_cpu(filters[i].element.flags) &

			   I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>

			   I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;



		/* Due to hardware eccentricities, the VNI for Geneve is shifted

		 * one more byte further than normally used for Tenant ID in

		 * other tunnel types.

		 */

		if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {

			ti = le32_to_cpu(filters[i].element.tenant_id);

			filters[i].element.tenant_id = cpu_to_le32(ti << 8);

		}

	}



	status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);



	return status;

}



/**

 * i40e_aq_rem_cloud_filters

 * @hw: pointer to the hardware structure

 * @seid: VSI seid to remove cloud filters from

 * @filters: Buffer which contains the filters to be removed

 * @filter_count: number of filters contained in the buffer

 *

 * Remove the cloud filters for a given VSI.  The contents of the

 * i40e_aqc_cloud_filters_element_data are filled in by the caller

 * of the function.

 *

 **/

enum i40e_status_code

i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,

			  struct i40e_aqc_cloud_filters_element_data *filters,

			  u8 filter_count)

{

	struct i40e_aq_desc desc;

	struct i40e_aqc_add_remove_cloud_filters *cmd =

	(struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;

	enum i40e_status_code status;

	u16 buff_len;



	i40e_fill_default_direct_cmd_desc(&desc,

					  i40e_aqc_opc_remove_cloud_filters);



	buff_len = filter_count * sizeof(*filters);

	desc.datalen = cpu_to_le16(buff_len);

	desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));

	cmd->num_filters = filter_count;

	cmd->seid = cpu_to_le16(seid);



	status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);



	return status;

}



/**

 * i40e_aq_rem_cloud_filters_bb

 * @hw: pointer to the hardware structure

 * @seid: VSI seid to remove cloud filters from

 * @filters: Buffer which contains the filters in big buffer to be removed

 * @filter_count: number of filters contained in the buffer

 *

 * Remove the big buffer cloud filters for a given VSI.  The contents of the

 * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the

 * function.

 *

 **/

i40e_status

i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,

			     struct i40e_aqc_cloud_filters_element_bb *filters,

			     u8 filter_count)

{

	struct i40e_aq_desc desc;

	struct i40e_aqc_add_remove_cloud_filters *cmd =

	(struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;

	i40e_status status;

	u16 buff_len;

	int i;



	i40e_fill_default_direct_cmd_desc(&desc,

					  i40e_aqc_opc_remove_cloud_filters);



	buff_len = filter_count * sizeof(*filters);

	desc.datalen = cpu_to_le16(buff_len);

	desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));

	cmd->num_filters = filter_count;

	cmd->seid = cpu_to_le16(seid);

	cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;



	for (i = 0; i < filter_count; i++) {

		u16 tnl_type;

		u32 ti;



		tnl_type = (le16_to_cpu(filters[i].element.flags) &

			   I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>

			   I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;



		/* Due to hardware eccentricities, the VNI for Geneve is shifted

		 * one more byte further than normally used for Tenant ID in

		 * other tunnel types.

		 */

		if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {

			ti = le32_to_cpu(filters[i].element.tenant_id);

			filters[i].element.tenant_id = cpu_to_le32(ti << 8);

		}

	}



	status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);



	return status;

	return status;

}
 
}

drivers/net/ethernet/intel/i40e/i40e_ethtool.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -4343,7 +4343,7 @@ flags_complete: 
			sw_flags = I40E_AQ_SET_SWITCH_CFG_PROMISC;

			sw_flags = I40E_AQ_SET_SWITCH_CFG_PROMISC;

		valid_flags = I40E_AQ_SET_SWITCH_CFG_PROMISC;

		valid_flags = I40E_AQ_SET_SWITCH_CFG_PROMISC;

		ret = i40e_aq_set_switch_config(&pf->hw, sw_flags, valid_flags,

		ret = i40e_aq_set_switch_config(&pf->hw, sw_flags, valid_flags,

						NULL);

						0, NULL);

		if (ret && pf->hw.aq.asq_last_status != I40E_AQ_RC_ESRCH) {

		if (ret && pf->hw.aq.asq_last_status != I40E_AQ_RC_ESRCH) {

			dev_info(&pf->pdev->dev,

			dev_info(&pf->pdev->dev,

				 "couldn't set switch config bits, err %s aq_err %s\n",

				 "couldn't set switch config bits, err %s aq_err %s\n",

drivers/net/ethernet/intel/i40e/i40e_main.c

+959 −42

File changed.

Preview size limit exceeded, changes collapsed.

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