Commit e85c9d0f authored by Leonard Crestez's avatar Leonard Crestez Committed by Shawn Guo
Browse files

arm64: dts: imx8mm: Add cpufreq properties 

This is very similar to imx8mq cpufreq-dt support.

Operating points are from datasheet:
https://www.nxp.com/docs/en/data-sheet/IMX8MMCEC.pdf



Higher opps were omitted (just like imx8mq) because it requires checking
speed grade from OCOTP fuses.

Signed-off-by: default avatarLeonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 7b2ac489

arch/arm64/boot/dts/freescale/imx8mm.dtsi

+30 −0
Original line number Diff line number Diff line
@@ -48,32 +48,44 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0>;

			clock-latency = <61036>; /* two CLK32 periods */

			clocks = <&clk IMX8MM_CLK_ARM>;

			enable-method = "psci";

			next-level-cache = <&A53_L2>;

			operating-points-v2 = <&a53_opp_table>;

		};



		A53_1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x1>;

			clock-latency = <61036>; /* two CLK32 periods */

			clocks = <&clk IMX8MM_CLK_ARM>;

			enable-method = "psci";

			next-level-cache = <&A53_L2>;

			operating-points-v2 = <&a53_opp_table>;

		};



		A53_2: cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x2>;

			clock-latency = <61036>; /* two CLK32 periods */

			clocks = <&clk IMX8MM_CLK_ARM>;

			enable-method = "psci";

			next-level-cache = <&A53_L2>;

			operating-points-v2 = <&a53_opp_table>;

		};



		A53_3: cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x3>;

			clock-latency = <61036>; /* two CLK32 periods */

			clocks = <&clk IMX8MM_CLK_ARM>;

			enable-method = "psci";

			next-level-cache = <&A53_L2>;

			operating-points-v2 = <&a53_opp_table>;

		};



		A53_L2: l2-cache0 {
@@ -81,6 +93,24 @@ 
		};

	};



	a53_opp_table: opp-table {

		compatible = "operating-points-v2";

		opp-shared;



		opp-1200000000 {

			opp-hz = /bits/ 64 <1200000000>;

			opp-microvolt = <850000>;

			clock-latency-ns = <150000>;

		};



		opp-1600000000 {

			opp-hz = /bits/ 64 <1600000000>;

			opp-microvolt = <900000>;

			clock-latency-ns = <150000>;

			opp-suspend;

		};

	};



	memory@40000000 {

		device_type = "memory";

		reg = <0x0 0x40000000 0 0x80000000>;

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