sh: Convert Dreamcast support from hw_interrupt_type to irq_chip

 */

#include <linux/irq.h>

#include <asm/io.h>

#include <linux/io.h>

#include <asm/irq.h>

#include <mach/sysasic.h>

/* Dreamcast System ASIC Hardware Events -

   The Dreamcast's System ASIC (a.k.a. Holly) is responsible for receiving

   hardware events from system peripherals and triggering an SH7750 IRQ.

   Hardware events can trigger IRQs 13, 11, or 9 depending on which bits are

   set in the Event Mask Registers (EMRs).  When a hardware event is

   triggered, it's corresponding bit in the Event Status Registers (ESRs)

   is set, and that bit should be rewritten to the ESR to acknowledge that

   event.

   There are three 32-bit ESRs located at 0xa05f8900 - 0xa05f6908.  Event

   types can be found in include/asm-sh/dreamcast/sysasic.h. There are three

   groups of EMRs that parallel the ESRs.  Each EMR group corresponds to an

   IRQ, so 0xa05f6910 - 0xa05f6918 triggers IRQ 13, 0xa05f6920 - 0xa05f6928

   triggers IRQ 11, and 0xa05f6930 - 0xa05f6938 triggers IRQ 9.

   In the kernel, these events are mapped to virtual IRQs so that drivers can

   respond to them as they would a normal interrupt.  In order to keep this

   mapping simple, the events are mapped as:

   6900/6910 - Events  0-31, IRQ 13

   6904/6924 - Events 32-63, IRQ 11

   6908/6938 - Events 64-95, IRQ  9

/*

 * Dreamcast System ASIC Hardware Events -

 *

 * The Dreamcast's System ASIC (a.k.a. Holly) is responsible for receiving

 * hardware events from system peripherals and triggering an SH7750 IRQ.

 * Hardware events can trigger IRQs 13, 11, or 9 depending on which bits are

 * set in the Event Mask Registers (EMRs).  When a hardware event is

 * triggered, its corresponding bit in the Event Status Registers (ESRs)

 * is set, and that bit should be rewritten to the ESR to acknowledge that

 * event.

 *

 * There are three 32-bit ESRs located at 0xa05f6900 - 0xa05f6908.  Event

 * types can be found in arch/sh/include/mach-dreamcast/mach/sysasic.h.

 * There are three groups of EMRs that parallel the ESRs.  Each EMR group

 * corresponds to an IRQ, so 0xa05f6910 - 0xa05f6918 triggers IRQ 13,

 * 0xa05f6920 - 0xa05f6928 triggers IRQ 11, and 0xa05f6930 - 0xa05f6938

 * triggers IRQ 9.

 *

 * In the kernel, these events are mapped to virtual IRQs so that drivers can

 * respond to them as they would a normal interrupt.  In order to keep this

 * mapping simple, the events are mapped as:

 *

 * 6900/6910 - Events  0-31, IRQ 13

 * 6904/6924 - Events 32-63, IRQ 11

 * 6908/6938 - Events 64-95, IRQ  9

 *

 */

#define ESR_BASE 0x005f6900    /* Base event status register */

#define EMR_BASE 0x005f6910    /* Base event mask register */

/* Helps us determine the EMR group that this event belongs to: 0 = 0x6910,

   1 = 0x6920, 2 = 0x6930; also determine the event offset */

/*

 * Helps us determine the EMR group that this event belongs to: 0 = 0x6910,

 * 1 = 0x6920, 2 = 0x6930; also determine the event offset.

 */

#define LEVEL(event) (((event) - HW_EVENT_IRQ_BASE) / 32)

/* Return the hardware event's bit positon within the EMR/ESR */

#define EVENT_BIT(event) (((event) - HW_EVENT_IRQ_BASE) & 31)

/* For each of these *_irq routines, the IRQ passed in is the virtual IRQ

   (logically mapped to the corresponding bit for the hardware event). */

/*

 * For each of these *_irq routines, the IRQ passed in is the virtual IRQ

 * (logically mapped to the corresponding bit for the hardware event).

 */

/* Disable the hardware event by masking its bit in its EMR */

static inline void disable_systemasic_irq(unsigned int irq)

}

/* Acknowledge a hardware event by writing its bit back to its ESR */

static void ack_systemasic_irq(unsigned int irq)

static void mask_ack_systemasic_irq(unsigned int irq)

{

	__u32 esr = ESR_BASE + (LEVEL(irq) << 2);

	disable_systemasic_irq(irq);

	outl((1 << EVENT_BIT(irq)), esr);

}

/* After a IRQ has been ack'd and responded to, it needs to be renabled */

static void end_systemasic_irq(unsigned int irq)

{

        if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))

                enable_systemasic_irq(irq);

}

static unsigned int startup_systemasic_irq(unsigned int irq)

{

        enable_systemasic_irq(irq);

        return 0;

}

static void shutdown_systemasic_irq(unsigned int irq)

{

        disable_systemasic_irq(irq);

}

struct hw_interrupt_type systemasic_int = {

        .typename       = "System ASIC",

        .startup        = startup_systemasic_irq,

        .shutdown       = shutdown_systemasic_irq,

        .enable         = enable_systemasic_irq,

        .disable        = disable_systemasic_irq,

        .ack            = ack_systemasic_irq,

        .end            = end_systemasic_irq,

struct irq_chip systemasic_int = {

	.name		= "System ASIC",

	.mask		= disable_systemasic_irq,

	.mask_ack	= mask_ack_systemasic_irq,

	.unmask		= enable_systemasic_irq,

};

/*

#include <asm/machvec.h>

#include <mach/sysasic.h>

extern struct hw_interrupt_type systemasic_int;

extern struct irq_chip systemasic_int;

extern void aica_time_init(void);

extern int gapspci_init(void);

extern int systemasic_irq_demux(int);

	/* Assign all virtual IRQs to the System ASIC int. handler */

	for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++)

		irq_desc[i].chip = &systemasic_int;

		set_irq_chip_and_handler(i, &systemasic_int,

					 handle_level_irq);

	board_time_init = aica_time_init;