Commit e84b7119 authored by Janakarajan Natarajan's avatar Janakarajan Natarajan Committed by Paolo Bonzini
Browse files

x86/msr: Add AMD Core Perf Extension MSRs 



Add the EventSelect and Counter MSRs for AMD Core Perf Extension.

Signed-off-by: default avatarJanakarajan Natarajan <Janakarajan.Natarajan@amd.com>
Acked-by: default avatarThomas Gleixner <tglx@linutronix.de>
Signed-off-by: default avatarRadim Krčmář <rkrcmar@redhat.com>
parent 0c7f650e

arch/x86/include/asm/msr-index.h

+14 −0
Original line number Diff line number Diff line
@@ -353,7 +353,21 @@ 


/* Fam 15h MSRs */

#define MSR_F15H_PERF_CTL		0xc0010200

#define MSR_F15H_PERF_CTL0		MSR_F15H_PERF_CTL

#define MSR_F15H_PERF_CTL1		(MSR_F15H_PERF_CTL + 2)

#define MSR_F15H_PERF_CTL2		(MSR_F15H_PERF_CTL + 4)

#define MSR_F15H_PERF_CTL3		(MSR_F15H_PERF_CTL + 6)

#define MSR_F15H_PERF_CTL4		(MSR_F15H_PERF_CTL + 8)

#define MSR_F15H_PERF_CTL5		(MSR_F15H_PERF_CTL + 10)



#define MSR_F15H_PERF_CTR		0xc0010201

#define MSR_F15H_PERF_CTR0		MSR_F15H_PERF_CTR

#define MSR_F15H_PERF_CTR1		(MSR_F15H_PERF_CTR + 2)

#define MSR_F15H_PERF_CTR2		(MSR_F15H_PERF_CTR + 4)

#define MSR_F15H_PERF_CTR3		(MSR_F15H_PERF_CTR + 6)

#define MSR_F15H_PERF_CTR4		(MSR_F15H_PERF_CTR + 8)

#define MSR_F15H_PERF_CTR5		(MSR_F15H_PERF_CTR + 10)



#define MSR_F15H_NB_PERF_CTL		0xc0010240

#define MSR_F15H_NB_PERF_CTR		0xc0010241

#define MSR_F15H_PTSC			0xc0010280

CRA Git | Maintained and supported by SUSTech CRA and CCSE