Commit e82da214 authored by Paul Mundt's avatar Paul Mundt
Browse files

sh: Track the CPU family in sh_cpuinfo. 



This adds a family member to struct sh_cpuinfo, which allows us to fall
back more on the probe routines to work out what sort of subtype we are
running on. This will be used by the CPU cache initialization code in
order to first do family-level initialization, followed by subtype-level
optimizations.

Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent aae4d142

arch/sh/include/asm/bugs.h

+12 −12
Original line number Diff line number Diff line
@@ -21,25 +21,25 @@ static void __init check_bugs(void) 


	current_cpu_data.loops_per_jiffy = loops_per_jiffy;



	switch (current_cpu_data.type) {

	case CPU_SH7619:

	switch (current_cpu_data.family) {

	case CPU_FAMILY_SH2:

		*p++ = '2';

		break;

	case CPU_SH7201 ... CPU_MXG:

	case CPU_FAMILY_SH2A:

		*p++ = '2';

		*p++ = 'a';

		break;

	case CPU_SH7705 ... CPU_SH7729:

	case CPU_FAMILY_SH3:

		*p++ = '3';

		break;

	case CPU_SH7750 ... CPU_SH4_501:

	case CPU_FAMILY_SH4:

		*p++ = '4';

		break;

	case CPU_SH7763 ... CPU_SHX3:

	case CPU_FAMILY_SH4A:

		*p++ = '4';

		*p++ = 'a';

		break;

	case CPU_SH7343 ... CPU_SH7366:

	case CPU_FAMILY_SH4AL_DSP:

		*p++ = '4';

		*p++ = 'a';

		*p++ = 'l';
@@ -48,15 +48,15 @@ static void __init check_bugs(void) 
		*p++ = 's';

		*p++ = 'p';

		break;

	case CPU_SH5_101 ... CPU_SH5_103:

	case CPU_FAMILY_SH5:

		*p++ = '6';

		*p++ = '4';

		break;

	case CPU_SH_NONE:

	case CPU_FAMILY_UNKNOWN:

		/*

		 * Specifically use CPU_SH_NONE rather than default:,

		 * so we're able to have the compiler whine about

		 * unhandled enumerations.

		 * Specifically use CPU_FAMILY_UNKNOWN rather than

		 * default:, so we're able to have the compiler whine

		 * about unhandled enumerations.

		 */

		break;

	}

arch/sh/include/asm/processor.h

+12 −1
Original line number Diff line number Diff line
@@ -44,6 +44,17 @@ enum cpu_type { 
	CPU_SH_NONE

};



enum cpu_family {

	CPU_FAMILY_SH2,

	CPU_FAMILY_SH2A,

	CPU_FAMILY_SH3,

	CPU_FAMILY_SH4,

	CPU_FAMILY_SH4A,

	CPU_FAMILY_SH4AL_DSP,

	CPU_FAMILY_SH5,

	CPU_FAMILY_UNKNOWN,

};



/*

 * TLB information structure

 *
@@ -61,7 +72,7 @@ struct tlb_info { 
};



struct sh_cpuinfo {

	unsigned int type;

	unsigned int type, family;

	int cut_major, cut_minor;

	unsigned long loops_per_jiffy;

	unsigned long asid_cache;

arch/sh/kernel/cpu/sh2/probe.c

+1 −0
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ int __init detect_cpu_and_cache_system(void) 
	 */

	boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED;

	boot_cpu_data.icache = boot_cpu_data.dcache;

	boot_cpu_data.family = CPU_FAMILY_SH2;



	return 0;

}

arch/sh/kernel/cpu/sh2a/probe.c

+2 −0
Original line number Diff line number Diff line
@@ -15,6 +15,8 @@ 


int __init detect_cpu_and_cache_system(void)

{

	boot_cpu_data.family			= CPU_FAMILY_SH2A;



	/* All SH-2A CPUs have support for 16 and 32-bit opcodes.. */

	boot_cpu_data.flags			|= CPU_HAS_OP32;

arch/sh/kernel/cpu/sh3/probe.c

+2 −0
Original line number Diff line number Diff line
@@ -107,5 +107,7 @@ int __uses_jump_to_uncached detect_cpu_and_cache_system(void) 
	boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED;

	boot_cpu_data.icache = boot_cpu_data.dcache;



	boot_cpu_data.family = CPU_FAMILY_SH3;



	return 0;

}

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