Commit e818d5ed authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm 

Pull ARM fixes from Russell King:
 "Another round of relatively small ARM fixes.

  Thomas spotted that the strex backoff delay bit was a disable bit, so
  it needed to be clear for this to work.  Vladimir spotted that using a
  restart block for the cache flush operation would return -EINTR, which
  userspace was not expecting.  Dmitry spotted that the auxiliary
  control register accesses for Xscale were not correct"

* 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm:
  ARM: 8226/1: cacheflush: get rid of restarting block
  ARM: 8222/1: mvebu: enable strex backoff delay
  ARM: 8216/1: xscale: correct auxiliary register in suspend/resume
parents 98e8d2e0 3f4aa45c

arch/arm/include/asm/thread_info.h

+0 −11
Original line number Diff line number Diff line
@@ -44,16 +44,6 @@ struct cpu_context_save { 
	__u32	extra[2];		/* Xscale 'acc' register, etc */

};



struct arm_restart_block {

	union {

		/* For user cache flushing */

		struct {

			unsigned long start;

			unsigned long end;

		} cache;

	};

};



/*

 * low level task data that entry.S needs immediate access to.

 * __switch_to() assumes cpu_context follows immediately after cpu_domain.
@@ -79,7 +69,6 @@ struct thread_info { 
	unsigned long		thumbee_state;	/* ThumbEE Handler Base register */

#endif

	struct restart_block	restart_block;

	struct arm_restart_block	arm_restart_block;

};



#define INIT_THREAD_INFO(tsk)						\

arch/arm/kernel/traps.c

+2 −29
Original line number Diff line number Diff line
@@ -533,8 +533,6 @@ static int bad_syscall(int n, struct pt_regs *regs) 
	return regs->ARM_r0;

}



static long do_cache_op_restart(struct restart_block *);



static inline int

__do_cache_op(unsigned long start, unsigned long end)

{
@@ -543,24 +541,8 @@ __do_cache_op(unsigned long start, unsigned long end) 
	do {

		unsigned long chunk = min(PAGE_SIZE, end - start);



		if (signal_pending(current)) {

			struct thread_info *ti = current_thread_info();



			ti->restart_block = (struct restart_block) {

				.fn	= do_cache_op_restart,

			};



			ti->arm_restart_block = (struct arm_restart_block) {

				{

					.cache = {

						.start	= start,

						.end	= end,

					},

				},

			};



			return -ERESTART_RESTARTBLOCK;

		}

		if (fatal_signal_pending(current))

			return 0;



		ret = flush_cache_user_range(start, start + chunk);

		if (ret)
@@ -573,15 +555,6 @@ __do_cache_op(unsigned long start, unsigned long end) 
	return 0;

}



static long do_cache_op_restart(struct restart_block *unused)

{

	struct arm_restart_block *restart_block;



	restart_block = &current_thread_info()->arm_restart_block;

	return __do_cache_op(restart_block->cache.start,

			     restart_block->cache.end);

}



static inline int

do_cache_op(unsigned long start, unsigned long end, int flags)

{

arch/arm/mm/proc-v7.S

+0 −2
Original line number Diff line number Diff line
@@ -270,7 +270,6 @@ __v7_pj4b_setup: 
/* Auxiliary Debug Modes Control 1 Register */

#define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */

#define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */

#define PJ4B_BCK_OFF_STREX (1 << 5) /* Enable the back off of STREX instr */

#define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */



/* Auxiliary Debug Modes Control 2 Register */
@@ -293,7 +292,6 @@ __v7_pj4b_setup: 
	/* Auxiliary Debug Modes Control 1 Register */

	mrc	p15, 1,	r0, c15, c1, 1

	orr     r0, r0, #PJ4B_CLEAN_LINE

	orr     r0, r0, #PJ4B_BCK_OFF_STREX

	orr     r0, r0, #PJ4B_INTER_PARITY

	bic	r0, r0, #PJ4B_STATIC_BP

	mcr	p15, 1,	r0, c15, c1, 1

arch/arm/mm/proc-xscale.S

+2 −2
Original line number Diff line number Diff line
@@ -535,7 +535,7 @@ ENTRY(cpu_xscale_do_suspend) 
	mrc	p15, 0, r5, c15, c1, 0	@ CP access reg

	mrc	p15, 0, r6, c13, c0, 0	@ PID

	mrc	p15, 0, r7, c3, c0, 0	@ domain ID

	mrc	p15, 0, r8, c1, c1, 0	@ auxiliary control reg

	mrc	p15, 0, r8, c1, c0, 1	@ auxiliary control reg

	mrc	p15, 0, r9, c1, c0, 0	@ control reg

	bic	r4, r4, #2		@ clear frequency change bit

	stmia	r0, {r4 - r9}		@ store cp regs
@@ -552,7 +552,7 @@ ENTRY(cpu_xscale_do_resume) 
	mcr	p15, 0, r6, c13, c0, 0	@ PID

	mcr	p15, 0, r7, c3, c0, 0	@ domain ID

	mcr	p15, 0, r1, c2, c0, 0	@ translation table base addr

	mcr	p15, 0, r8, c1, c1, 0	@ auxiliary control reg

	mcr	p15, 0, r8, c1, c0, 1	@ auxiliary control reg

	mov	r0, r9			@ control register

	b	cpu_resume_mmu

ENDPROC(cpu_xscale_do_resume)

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