Commit e8121d98 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-spreadtrum', 'clk-stm32f', 'clk-stm32mp1', 'clk-hi655x'... 

Merge branches 'clk-spreadtrum', 'clk-stm32f', 'clk-stm32mp1', 'clk-hi655x' and 'clk-gpio' into clk-next

* clk-spreadtrum:
  clk: sprd: add RTC gate for SC9860
  dt-bindings: clocks: add APB RTC gate for SC9860

* clk-stm32f:
  clk: stm32: Add clk entry for SDMMC2 on stm32F769
  clk: stm32: Add DSI clock for STM32F469 Board
  clk: stm32: END_PRIMARY_CLK should be declare after CLK_SYSCLK

* clk-stm32mp1:
  clk: stm32: add configuration flags for each of the stm32 drivers
  clk: stm32mp1: add Debug clocks
  clk: stm32mp1: add MCO clocks
  clk: stm32mp1: add RTC clock
  clk: stm32mp1: add Peripheral & Kernel Clocks
  clk: stm32mp1: add Kernel timers
  clk: stm32mp1: add Sub System clocks
  clk: stm32mp1: add Post-dividers for PLL
  clk: stm32mp1: add PLL clocks
  clk: stm32mp1: add Source Clocks for PLLs
  clk: stm32mp1: add MP1 gate for hse/hsi/csi oscillators
  clk: stm32mp1: Introduce STM32MP1 clock driver
  dt-bindings: Document STM32MP1 Reset Clock Controller (RCC) bindings

* clk-hi655x:
  clk: enable hi655x common clk automatically

* clk-gpio:
  clk: clk-gpio: Allow GPIO to sleep in set/get_parent
parents caa9f3b7 b3316a67 f9acf105 da32d353 3a49afb8 2e838e7f

Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt

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+60 −0
Original line number Diff line number Diff line 
STMicroelectronics STM32 Peripheral Reset Clock Controller

==========================================================



The RCC IP is both a reset and a clock controller.



RCC makes also power management (resume/supend and wakeup interrupt).



Please also refer to reset.txt for common reset controller binding usage.



Please also refer to clock-bindings.txt for common clock controller

binding usage.





Required properties:

- compatible: "st,stm32mp1-rcc", "syscon"

- reg: should be register base and length as documented in the datasheet

- #clock-cells: 1, device nodes should specify the clock in their

  "clocks" property, containing a phandle to the clock device node,

  an index specifying the clock to use.

- #reset-cells: Shall be 1

- interrupts: Should contain a general interrupt line and a interrupt line

  to the wake-up of processor (CSTOP).



Example:

	rcc: rcc@50000000 {

		compatible = "st,stm32mp1-rcc", "syscon";

		reg = <0x50000000 0x1000>;

		#clock-cells = <1>;

		#reset-cells = <1>;

		interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>,

			     <GIC_SPI 145 IRQ_TYPE_NONE>;

	};



Specifying clocks

=================



All available clocks are defined as preprocessor macros in

dt-bindings/clock/stm32mp1-clks.h header and can be used in device

tree sources.



Specifying softreset control of devices

=======================================



Device nodes should specify the reset channel required in their "resets"

property, containing a phandle to the reset device node and an index specifying

which channel to use.

The index is the bit number within the RCC registers bank, starting from RCC

base address.

It is calculated as: index = register_offset / 4 * 32 + bit_offset.

Where bit_offset is the bit offset within the register.



For example on STM32MP1, for LTDC reset:

 ltdc = APB4_RSTSETR_offset / 4 * 32 + LTDC_bit_offset

      = 0x180 / 4 * 32 + 0 = 3072



The list of valid indices for STM32MP1 is available in:

include/dt-bindings/reset-controller/stm32mp1-resets.h



This file implements defines like:

#define LTDC_R	3072

drivers/clk/Kconfig

+24 −2
Original line number Diff line number Diff line
@@ -55,8 +55,10 @@ config COMMON_CLK_RK808 
	  by control register.



config COMMON_CLK_HI655X

	tristate "Clock driver for Hi655x"

	depends on MFD_HI655X_PMIC || COMPILE_TEST

	tristate "Clock driver for Hi655x" if EXPERT

	depends on (MFD_HI655X_PMIC || COMPILE_TEST)

	depends on REGMAP

	default MFD_HI655X_PMIC

	---help---

	  This driver supports the hi655x PMIC clock. This

	  multi-function device has one fixed-rate oscillator, clocked
@@ -238,6 +240,26 @@ config COMMON_CLK_VC5 
	  This driver supports the IDT VersaClock 5 and VersaClock 6

	  programmable clock generators.



config COMMON_CLK_STM32MP157

	def_bool COMMON_CLK && MACH_STM32MP157

	help

	---help---

	  Support for stm32mp157 SoC family clocks



config COMMON_CLK_STM32F

	bool "Clock driver for stm32f4 and stm32f7 SoC families"

	depends on MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746

	help

	---help---

	  Support for stm32f4 and stm32f7 SoC families clocks



config COMMON_CLK_STM32H7

	bool "Clock driver for stm32h7 SoC family"

	depends on MACH_STM32H743

	help

	---help---

	  Support for stm32h7 SoC family clocks



source "drivers/clk/bcm/Kconfig"

source "drivers/clk/hisilicon/Kconfig"

source "drivers/clk/imgtec/Kconfig"

drivers/clk/Makefile

+3 −2
Original line number Diff line number Diff line
@@ -45,8 +45,9 @@ obj-$(CONFIG_COMMON_CLK_SCPI) += clk-scpi.o 
obj-$(CONFIG_COMMON_CLK_SI5351)		+= clk-si5351.o

obj-$(CONFIG_COMMON_CLK_SI514)		+= clk-si514.o

obj-$(CONFIG_COMMON_CLK_SI570)		+= clk-si570.o

obj-$(CONFIG_ARCH_STM32)		+= clk-stm32f4.o

obj-$(CONFIG_ARCH_STM32)		+= clk-stm32h7.o

obj-$(CONFIG_COMMON_CLK_STM32F)		+= clk-stm32f4.o

obj-$(CONFIG_COMMON_CLK_STM32H7)	+= clk-stm32h7.o

obj-$(CONFIG_COMMON_CLK_STM32MP157)	+= clk-stm32mp1.o

obj-$(CONFIG_ARCH_TANGO)		+= clk-tango4.o

obj-$(CONFIG_CLK_TWL6040)		+= clk-twl6040.o

obj-$(CONFIG_ARCH_U300)			+= clk-u300.o

drivers/clk/clk-gpio.c

+2 −2
Original line number Diff line number Diff line
@@ -73,14 +73,14 @@ static u8 clk_gpio_mux_get_parent(struct clk_hw *hw) 
{

	struct clk_gpio *clk = to_clk_gpio(hw);



	return gpiod_get_value(clk->gpiod);

	return gpiod_get_value_cansleep(clk->gpiod);

}



static int clk_gpio_mux_set_parent(struct clk_hw *hw, u8 index)

{

	struct clk_gpio *clk = to_clk_gpio(hw);



	gpiod_set_value(clk->gpiod, index);

	gpiod_set_value_cansleep(clk->gpiod, index);



	return 0;

}

drivers/clk/clk-stm32f4.c

+12 −2
Original line number Diff line number Diff line
@@ -282,6 +282,7 @@ static const struct stm32f4_gate_data stm32f746_gates[] __initconst = { 


	{ STM32F4_RCC_APB2ENR,  0,	"tim1",		"apb2_mul" },

	{ STM32F4_RCC_APB2ENR,  1,	"tim8",		"apb2_mul" },

	{ STM32F4_RCC_APB2ENR,  7,	"sdmmc2",	"sdmux"    },

	{ STM32F4_RCC_APB2ENR,  8,	"adc1",		"apb2_div" },

	{ STM32F4_RCC_APB2ENR,  9,	"adc2",		"apb2_div" },

	{ STM32F4_RCC_APB2ENR, 10,	"adc3",		"apb2_div" },
@@ -315,7 +316,7 @@ static const u64 stm32f46xx_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull, 


static const u64 stm32f746_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,

						      0x0000000000000003ull,

						      0x04f77f033e01c9ffull };

						      0x04f77f833e01c9ffull };



static const u64 *stm32f4_gate_map;
@@ -521,7 +522,7 @@ static const struct stm32f4_pll_data stm32f429_pll[MAX_PLL_DIV] = { 
};



static const struct stm32f4_pll_data stm32f469_pll[MAX_PLL_DIV] = {

	{ PLL,	   50, { "pll",	     "pll-q",    NULL	    } },

	{ PLL,	   50, { "pll",	     "pll-q",    "pll-r"    } },

	{ PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } },

	{ PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } },

};
@@ -1047,6 +1048,8 @@ static const char *rtc_parents[4] = { 
	"no-clock", "lse", "lsi", "hse-rtc"

};



static const char *dsi_parent[2] = { NULL, "pll-r" };



static const char *lcd_parent[1] = { "pllsai-r-div" };



static const char *i2s_parents[2] = { "plli2s-r", NULL };
@@ -1156,6 +1159,12 @@ static const struct stm32_aux_clk stm32f469_aux_clk[] = { 
		NO_GATE, 0,

		0

	},

	{

		CLK_F469_DSI, "dsi", dsi_parent, ARRAY_SIZE(dsi_parent),

		STM32F4_RCC_DCKCFGR, 29, 1,

		STM32F4_RCC_APB2ENR, 27,

		CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT

	},

};



static const struct stm32_aux_clk stm32f746_aux_clk[] = {
@@ -1450,6 +1459,7 @@ static void __init stm32f4_rcc_init(struct device_node *np) 
	stm32f4_gate_map = data->gates_map;



	hse_clk = of_clk_get_parent_name(np, 0);

	dsi_parent[0] = hse_clk;



	i2s_in_clk = of_clk_get_parent_name(np, 1);

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