Commit e7fd28a7 authored by Peter Zijlstra's avatar Peter Zijlstra Committed by Ingo Molnar
Browse files

asm-generic/tlb, arch: Provide generic VIPT cache flush 

The one obvious thing SH and ARM want is a sensible default for
tlb_start_vma(). (also: https://lkml.org/lkml/2004/1/15/6

 )

Avoid all VIPT architectures providing their own tlb_start_vma()
implementation and rely on architectures to provide a no-op
flush_cache_range() when it is not relevant.

This patch makes tlb_start_vma() default to flush_cache_range(), which
should be right and sufficient. The only exceptions that I found where
(oddly):

  - m68k-mmu
  - sparc64
  - unicore

Those architectures appear to have flush_cache_range(), but their
current tlb_start_vma() does not call it.

No change in behavior intended.

Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: default avatarWill Deacon <will.deacon@arm.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: David Miller <davem@davemloft.net>
Cc: Guan Xuetao <gxt@pku.edu.cn>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Nick Piggin <npiggin@gmail.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Rik van Riel <riel@surriel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent ed6a7935

arch/arc/include/asm/tlb.h

+0 −9
Original line number Diff line number Diff line
@@ -23,15 +23,6 @@ do { \ 
 *

 * Note, read http://lkml.org/lkml/2004/1/15/6

 */

#ifndef CONFIG_ARC_CACHE_VIPT_ALIASING

#define tlb_start_vma(tlb, vma)

#else

#define tlb_start_vma(tlb, vma)						\

do {									\

	if (!tlb->fullmm)						\

		flush_cache_range(vma, vma->vm_start, vma->vm_end);	\

} while(0)

#endif



#define tlb_end_vma(tlb, vma)						\

do {									\

arch/mips/include/asm/tlb.h

+0 −9
Original line number Diff line number Diff line
@@ -5,15 +5,6 @@ 
#include <asm/cpu-features.h>

#include <asm/mipsregs.h>



/*

 * MIPS doesn't need any special per-pte or per-vma handling, except

 * we need to flush cache for area to be unmapped.

 */

#define tlb_start_vma(tlb, vma)					\

	do {							\

		if (!tlb->fullmm)				\

			flush_cache_range(vma, vma->vm_start, vma->vm_end); \

	}  while (0)

#define tlb_end_vma(tlb, vma) do { } while (0)

#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)

arch/nds32/include/asm/tlb.h

+0 −6
Original line number Diff line number Diff line
@@ -4,12 +4,6 @@ 
#ifndef __ASMNDS32_TLB_H

#define __ASMNDS32_TLB_H



#define tlb_start_vma(tlb,vma)						\

	do {								\

		if (!tlb->fullmm)					\

			flush_cache_range(vma, vma->vm_start, vma->vm_end); \

	} while (0)



#define tlb_end_vma(tlb,vma)				\

	do { 						\

		if(!tlb->fullmm)			\

arch/nios2/include/asm/tlb.h

+0 −10
Original line number Diff line number Diff line
@@ -15,16 +15,6 @@ 


extern void set_mmu_pid(unsigned long pid);



/*

 * NiosII doesn't need any special per-pte or per-vma handling, except

 * we need to flush cache for the area to be unmapped.

 */

#define tlb_start_vma(tlb, vma)					\

	do {							\

		if (!tlb->fullmm)				\

			flush_cache_range(vma, vma->vm_start, vma->vm_end); \

	}  while (0)



#define tlb_end_vma(tlb, vma)	do { } while (0)

#define __tlb_remove_tlb_entry(tlb, ptep, address)	do { } while (0)

arch/parisc/include/asm/tlb.h

+0 −5
Original line number Diff line number Diff line
@@ -7,11 +7,6 @@ do { if ((tlb)->fullmm) \ 
		flush_tlb_mm((tlb)->mm);\

} while (0)



#define tlb_start_vma(tlb, vma) \

do {	if (!(tlb)->fullmm)	\

		flush_cache_range(vma, vma->vm_start, vma->vm_end); \

} while (0)



#define tlb_end_vma(tlb, vma)	\

do {	if (!(tlb)->fullmm)	\

		flush_tlb_range(vma, vma->vm_start, vma->vm_end); \

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