Merge tag 'drm-next-5.4-2019-08-09' of git://people.freedesktop.org/~agd5f/linux into drm-next

F:	include/linux/amd-iommu.h

AMD KFD

M:	Oded Gabbay <oded.gabbay@gmail.com>

L:	dri-devel@lists.freedesktop.org

T:	git git://people.freedesktop.org/~gabbayo/linux.git

S:	Supported

F:	drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

F:	drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h

F:	drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

F:	drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

F:	drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

F:	drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c

F:	drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

M:	Felix Kuehling <Felix.Kuehling@amd.com>

L:	amd-gfx@lists.freedesktop.org

T:	git git://people.freedesktop.org/~agd5f/linux

S:	Supported

F:	drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd*.[ch]

F:	drivers/gpu/drm/amd/amdkfd/

F:	drivers/gpu/drm/amd/include/cik_structs.h

F:	drivers/gpu/drm/amd/include/kgd_kfd_interface.h

amdgpu-y += \

	vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \

	vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o

	vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \

	arct_reg_init.o navi12_reg_init.o

# add DF block

amdgpu-y += \

amdgpu-y += \

	gmc_v7_0.o \

	gmc_v8_0.o \

	gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o gfxhub_v1_1.o \

	gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o gfxhub_v1_1.o mmhub_v9_4.o \

	gfxhub_v2_0.o mmhub_v2_0.o gmc_v10_0.o

# add UMC block

amdgpu-y += \

	umc_v6_1.o

# add IH block

amdgpu-y += \

	amdgpu_irq.o \

amdgpu-y += \

	amdgpu_vcn.o \

	vcn_v1_0.o \

	vcn_v2_0.o

	vcn_v2_0.o \

	vcn_v2_5.o

# add ATHUB block

amdgpu-y += \

	 amdgpu_amdkfd_gpuvm.o \

	 amdgpu_amdkfd_gfx_v8.o \

	 amdgpu_amdkfd_gfx_v9.o \

	 amdgpu_amdkfd_arcturus.o \

	 amdgpu_amdkfd_gfx_v10.o

ifneq ($(CONFIG_DRM_AMDGPU_CIK),)

#include "amdgpu_smu.h"

#include "amdgpu_discovery.h"

#include "amdgpu_mes.h"

#include "amdgpu_umc.h"

#define MAX_GPU_INSTANCE		16

	bool grbm_indexed;

};

enum amd_reset_method {

	AMD_RESET_METHOD_LEGACY = 0,

	AMD_RESET_METHOD_MODE0,

	AMD_RESET_METHOD_MODE1,

	AMD_RESET_METHOD_MODE2,

	AMD_RESET_METHOD_BACO

};

/*

 * ASIC specific functions.

 */

			     u32 sh_num, u32 reg_offset, u32 *value);

	void (*set_vga_state)(struct amdgpu_device *adev, bool state);

	int (*reset)(struct amdgpu_device *adev);

	enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);

	/* get the reference clock */

	u32 (*get_xclk)(struct amdgpu_device *adev);

	/* MM block clocks */

typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);

typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);

typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);

typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);

typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);

typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);

	u32 ref_and_mask_cp9;

	u32 ref_and_mask_sdma0;

	u32 ref_and_mask_sdma1;

	u32 ref_and_mask_sdma2;

	u32 ref_and_mask_sdma3;

	u32 ref_and_mask_sdma4;

	u32 ref_and_mask_sdma5;

	u32 ref_and_mask_sdma6;

	u32 ref_and_mask_sdma7;

};

struct amdgpu_mmio_remap {

	void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,

			bool use_doorbell, int doorbell_index, int doorbell_size);

	void (*vcn_doorbell_range)(struct amdgpu_device *adev, bool use_doorbell,

			int doorbell_index);

				   int doorbell_index, int instance);

	void (*enable_doorbell_aperture)(struct amdgpu_device *adev,

					 bool enable);

	void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,

					 int is_disable);

	void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config,

					 uint64_t *count);

	uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val);

	void (*set_fica)(struct amdgpu_device *adev, uint32_t ficaa_val,

			 uint32_t ficadl_val, uint32_t ficadh_val);

};

/* Define the HW IP blocks will be used in driver , add more if necessary */

enum amd_hw_ip_block_type {

	HDP_HWIP,

	SDMA0_HWIP,

	SDMA1_HWIP,

	SDMA2_HWIP,

	SDMA3_HWIP,

	SDMA4_HWIP,

	SDMA5_HWIP,

	SDMA6_HWIP,

	SDMA7_HWIP,

	MMHUB_HWIP,

	ATHUB_HWIP,

	NBIO_HWIP,

	NBIF_HWIP,

	THM_HWIP,

	CLK_HWIP,

	UMC_HWIP,

	RSMU_HWIP,

	MAX_HWIP

};

#define HWIP_MAX_INSTANCE	6

#define HWIP_MAX_INSTANCE	8

struct amd_powerplay {

	void *pp_handle;

	amdgpu_wreg_t			pcie_wreg;

	amdgpu_rreg_t			pciep_rreg;

	amdgpu_wreg_t			pciep_wreg;

	amdgpu_rreg64_t			pcie_rreg64;

	amdgpu_wreg64_t			pcie_wreg64;

	/* protects concurrent UVD register access */

	spinlock_t uvd_ctx_idx_lock;

	amdgpu_rreg_t			uvd_ctx_rreg;

	dma_addr_t			dummy_page_addr;

	struct amdgpu_vm_manager	vm_manager;

	struct amdgpu_vmhub             vmhub[AMDGPU_MAX_VMHUBS];

	unsigned			num_vmhubs;

	/* memory management */

	struct amdgpu_mman		mman;

	/* KFD */

	struct amdgpu_kfd_dev		kfd;

	/* UMC */

	struct amdgpu_umc		umc;

	/* display related functionality */

	struct amdgpu_display_manager dm;

	/* record last mm index being written through WREG32*/

	unsigned long last_mm_index;

	bool                            in_gpu_reset;

	enum pp_mp1_state               mp1_state;

	struct mutex  lock_reset;

	struct amdgpu_doorbell_index doorbell_index;

#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))

#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))

#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))

#define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))

#define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))

#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))

#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))

#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))

 */

#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))

#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))

#define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))

#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))

#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))

#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))

	case CHIP_RAVEN:

		kfd2kgd = amdgpu_amdkfd_gfx_9_0_get_functions();

		break;

	case CHIP_ARCTURUS:

		kfd2kgd = amdgpu_amdkfd_arcturus_get_functions();

		break;

	case CHIP_NAVI10:

	case CHIP_NAVI14:

	case CHIP_NAVI12:

		kfd2kgd = amdgpu_amdkfd_gfx_10_0_get_functions();

		break;

	default:

{

	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;

	if (adev->powerplay.pp_funcs &&

	if (is_support_sw_smu(adev))

		smu_switch_power_profile(&adev->smu,

					 PP_SMC_POWER_PROFILE_COMPUTE,

					 !idle);

	else if (adev->powerplay.pp_funcs &&

		 adev->powerplay.pp_funcs->switch_power_profile)

		amdgpu_dpm_switch_power_profile(adev,

						PP_SMC_POWER_PROFILE_COMPUTE,

	return NULL;

}

struct kfd2kgd_calls *amdgpu_amdkfd_arcturus_get_functions(void)

{

	return NULL;

}

struct kfd2kgd_calls *amdgpu_amdkfd_gfx_10_0_get_functions(void)

{

	return NULL;

struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void);

struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void);

struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void);

struct kfd2kgd_calls *amdgpu_amdkfd_arcturus_get_functions(void);

struct kfd2kgd_calls *amdgpu_amdkfd_gfx_10_0_get_functions(void);

bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid);