Commit e7f5c9a1 authored by Tomi Valkeinen's avatar Tomi Valkeinen
Browse files

Merge tag 'omapdss-for-3.8' of git://gitorious.org/linux-omap-dss2/linux into for-linus 

OMAPDSS changes for 3.8, including:
- use dynanic debug prints
- OMAP platform dependency removals
- Creation of compat-layer, helping us to improve omapdrm
- Misc cleanups, aiming to make omadss more in line with the upcoming common
  display framework

* tag 'omapdss-for-3.8' of git://gitorious.org/linux-omap-dss2/linux: (140 commits)
  OMAPDSS: fix TV-out issue with DSI PLL
  Revert "OMAPFB: simplify locking"
  OMAPFB: remove silly loop in fb2display()
  OMAPFB: fix error handling in omapfb_find_best_mode()
  OMAPFB: use devm_kzalloc to allocate omapfb2_device
  OMAPDSS: DISPC: remove dispc fck uses
  OMAPDSS: DISPC: get dss clock rate from dss driver
  OMAPDSS: use omapdss_compat_init() in other drivers
  OMAPDSS: export dispc functions
  OMAPDSS: export dss_feat functions
  OMAPDSS: export dss_mgr_ops functions
  OMAPDSS: separate compat files in the Makefile
  OMAPDSS: move display sysfs init to compat layer
  OMAPDSS: DPI: use dispc's check_timings
  OMAPDSS: DISPC: add dispc_ovl_check()
  OMAPDSS: move irq handling to dispc-compat
  OMAPDSS: move omap_dispc_wait_for_irq_interruptible_timeout to dispc-compat.c
  OMAPDSS: move blocking mgr enable/disable to compat layer
  OMAPDSS: manage framedone irq with mgr ops
  OMAPDSS: add manager ops
  ...
parents a240af2e bd0f5cc3

Documentation/arm/OMAP/DSS

+4 −6
Original line number Original line Diff line number Diff line
@@ -285,7 +285,10 @@ FB0 +-- GFX ---- LCD ---- LCD 
Misc notes

Misc notes

----------

----------





OMAP FB allocates the framebuffer memory using the OMAP VRAM allocator.

OMAP FB allocates the framebuffer memory using the standard dma allocator. You

can enable Contiguous Memory Allocator (CONFIG_CMA) to improve the dma

allocator, and if CMA is enabled, you use "cma=" kernel parameter to increase

the global memory area for CMA.





Using DSI DPLL to generate pixel clock it is possible produce the pixel clock

Using DSI DPLL to generate pixel clock it is possible produce the pixel clock

of 86.5MHz (max possible), and with that you get 1280x1024@57 output from DVI.

of 86.5MHz (max possible), and with that you get 1280x1024@57 output from DVI.
@@ -301,11 +304,6 @@ framebuffer parameters. 
Kernel boot arguments

Kernel boot arguments

---------------------

---------------------





vram=<size>[,<physaddr>]

	- Amount of total VRAM to preallocate and optionally a physical start

	  memory address. For example, "10M". omapfb allocates memory for

	  framebuffers from VRAM.



omapfb.mode=<display>:<mode>[,...]

omapfb.mode=<display>:<mode>[,...]

	- Default video mode for specified displays. For example,

	- Default video mode for specified displays. For example,

	  "dvi:800x400MR-24@60".  See drivers/video/modedb.c.

	  "dvi:800x400MR-24@60".  See drivers/video/modedb.c.

arch/arm/mach-omap2/board-rx51-video.c

+0 −14
Original line number Original line Diff line number Diff line
@@ -16,7 +16,6 @@ 
#include <linux/mm.h>

#include <linux/mm.h>

#include <asm/mach-types.h>

#include <asm/mach-types.h>

#include <video/omapdss.h>

#include <video/omapdss.h>

#include <plat/vram.h>

#include <linux/platform_data/spi-omap2-mcspi.h>

#include <linux/platform_data/spi-omap2-mcspi.h>





#include "board-rx51.h"

#include "board-rx51.h"
@@ -87,17 +86,4 @@ static int __init rx51_video_init(void) 
}

}





subsys_initcall(rx51_video_init);

subsys_initcall(rx51_video_init);



void __init rx51_video_mem_init(void)

{

	/*

	 * GFX 864x480x32bpp

	 * VID1/2 1280x720x32bpp double buffered

	 */

	omap_vram_set_sdram_vram(PAGE_ALIGN(864 * 480 * 4) +

			2 * PAGE_ALIGN(1280 * 720 * 4 * 2), 0);

}



#else

void __init rx51_video_mem_init(void) { }

#endif /* defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) */
 
#endif /* defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) */

arch/arm/mach-omap2/board-rx51.c

+0 −3
Original line number Original line Diff line number Diff line
@@ -34,8 +34,6 @@ 




#define RX51_GPIO_SLEEP_IND 162

#define RX51_GPIO_SLEEP_IND 162





extern void rx51_video_mem_init(void);



static struct gpio_led gpio_leds[] = {

static struct gpio_led gpio_leds[] = {

	{

	{

		.name	= "sleep_ind",

		.name	= "sleep_ind",
@@ -112,7 +110,6 @@ static void __init rx51_init(void) 




static void __init rx51_reserve(void)

static void __init rx51_reserve(void)

{

{

	rx51_video_mem_init();

	omap_reserve();

	omap_reserve();

}

}

arch/arm/mach-omap2/display.c

+48 −5
Original line number Original line Diff line number Diff line
@@ -100,17 +100,20 @@ static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = { 
	{ "dss_hdmi", "omapdss_hdmi", -1 },

	{ "dss_hdmi", "omapdss_hdmi", -1 },

};

};





static void __init omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)

static void __init omap4_tpd12s015_mux_pads(void)

{

{

	u32 reg;

	u16 control_i2c_1;



	omap_mux_init_signal("hdmi_cec",

	omap_mux_init_signal("hdmi_cec",

			OMAP_PIN_INPUT_PULLUP);

			OMAP_PIN_INPUT_PULLUP);

	omap_mux_init_signal("hdmi_ddc_scl",

	omap_mux_init_signal("hdmi_ddc_scl",

			OMAP_PIN_INPUT_PULLUP);

			OMAP_PIN_INPUT_PULLUP);

	omap_mux_init_signal("hdmi_ddc_sda",

	omap_mux_init_signal("hdmi_ddc_sda",

			OMAP_PIN_INPUT_PULLUP);

			OMAP_PIN_INPUT_PULLUP);

}



static void __init omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)

{

	u32 reg;

	u16 control_i2c_1;





	/*

	/*

	 * CONTROL_I2C_1: HDMI_DDC_SDA_PULLUPRESX (bit 28) and

	 * CONTROL_I2C_1: HDMI_DDC_SDA_PULLUPRESX (bit 28) and
@@ -161,8 +164,10 @@ static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes) 




int __init omap_hdmi_init(enum omap_hdmi_flags flags)

int __init omap_hdmi_init(enum omap_hdmi_flags flags)

{

{

	if (cpu_is_omap44xx())

	if (cpu_is_omap44xx()) {

		omap4_hdmi_mux_pads(flags);

		omap4_hdmi_mux_pads(flags);

		omap4_tpd12s015_mux_pads();

	}





	return 0;

	return 0;

}

}
@@ -284,6 +289,35 @@ err: 
	return ERR_PTR(r);

	return ERR_PTR(r);

}

}





static enum omapdss_version __init omap_display_get_version(void)

{

	if (cpu_is_omap24xx())

		return OMAPDSS_VER_OMAP24xx;

	else if (cpu_is_omap3630())

		return OMAPDSS_VER_OMAP3630;

	else if (cpu_is_omap34xx()) {

		if (soc_is_am35xx()) {

			return OMAPDSS_VER_AM35xx;

		} else {

			if (omap_rev() < OMAP3430_REV_ES3_0)

				return OMAPDSS_VER_OMAP34xx_ES1;

			else

				return OMAPDSS_VER_OMAP34xx_ES3;

		}

	} else if (omap_rev() == OMAP4430_REV_ES1_0)

		return OMAPDSS_VER_OMAP4430_ES1;

	else if (omap_rev() == OMAP4430_REV_ES2_0 ||

			omap_rev() == OMAP4430_REV_ES2_1 ||

			omap_rev() == OMAP4430_REV_ES2_2)

		return OMAPDSS_VER_OMAP4430_ES2;

	else if (cpu_is_omap44xx())

		return OMAPDSS_VER_OMAP4;

	else if (soc_is_omap54xx())

		return OMAPDSS_VER_OMAP5;

	else

		return OMAPDSS_VER_UNKNOWN;

}



int __init omap_display_init(struct omap_dss_board_info *board_data)

int __init omap_display_init(struct omap_dss_board_info *board_data)

{

{

	int r = 0;

	int r = 0;
@@ -291,9 +325,18 @@ int __init omap_display_init(struct omap_dss_board_info *board_data) 
	int i, oh_count;

	int i, oh_count;

	const struct omap_dss_hwmod_data *curr_dss_hwmod;

	const struct omap_dss_hwmod_data *curr_dss_hwmod;

	struct platform_device *dss_pdev;

	struct platform_device *dss_pdev;

	enum omapdss_version ver;





	/* create omapdss device */

	/* create omapdss device */





	ver = omap_display_get_version();



	if (ver == OMAPDSS_VER_UNKNOWN) {

		pr_err("DSS not supported on this SoC\n");

		return -ENODEV;

	}



	board_data->version = ver;

	board_data->dsi_enable_pads = omap_dsi_enable_pads;

	board_data->dsi_enable_pads = omap_dsi_enable_pads;

	board_data->dsi_disable_pads = omap_dsi_disable_pads;

	board_data->dsi_disable_pads = omap_dsi_disable_pads;

	board_data->get_context_loss_count = omap_pm_get_dev_context_loss_count;

	board_data->get_context_loss_count = omap_pm_get_dev_context_loss_count;

arch/arm/mach-omap2/sdrc.c

+0 −16
Original line number Original line Diff line number Diff line
@@ -160,19 +160,3 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0, 
	sdrc_write_reg(l, SDRC_POWER);

	sdrc_write_reg(l, SDRC_POWER);

	omap2_sms_save_context();

	omap2_sms_save_context();

}
 
}
 


void omap2_sms_write_rot_control(u32 val, unsigned ctx)

{

	sms_write_reg(val, SMS_ROT_CONTROL(ctx));

}



void omap2_sms_write_rot_size(u32 val, unsigned ctx)

{

	sms_write_reg(val, SMS_ROT_SIZE(ctx));

}



void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx)

{

	sms_write_reg(val, SMS_ROT_PHYSICAL_BA(ctx));

}

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