Commit e7ecbc05 authored by Masahiro Yamada's avatar Masahiro Yamada Committed by Olof Johansson
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ARM: uniphier: add outer cache support 



This commit adds support for UniPhier outer cache controller.
All the UniPhier SoCs are equipped with the L2 cache, while the L3
cache is currently only integrated on PH1-Pro5 SoC.

Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parent 156746b1

Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt

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UniPhier outer cache controller



UniPhier SoCs are integrated with a full-custom outer cache controller system.

All of them have a level 2 cache controller, and some have a level 3 cache

controller as well.



Required properties:

- compatible: should be "socionext,uniphier-system-cache"

- reg: offsets and lengths of the register sets for the device.  It should

  contain 3 regions: control register, revision register, operation register,

  in this order.

- cache-unified: specifies the cache is a unified cache.

- cache-size: specifies the size in bytes of the cache

- cache-sets: specifies the number of associativity sets of the cache

- cache-line-size: specifies the line size in bytes

- cache-level: specifies the level in the cache hierarchy.  The value should

  be 2 for L2 cache, 3 for L3 cache, etc.



Optional properties:

- next-level-cache: phandle to the next level cache if present.  The next level

  cache should be also compatible with "socionext,uniphier-system-cache".



The L2 cache must exist to use the L3 cache; the cache hierarchy must be

indicated correctly with "next-level-cache" properties.



Example 1 (system with L2):

	l2: l2-cache@500c0000 {

		compatible = "socionext,uniphier-system-cache";

		reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,

		      <0x506c0000 0x400>;

		cache-unified;

		cache-size = <0x80000>;

		cache-sets = <256>;

		cache-line-size = <128>;

		cache-level = <2>;

	};



Example 2 (system with L2 and L3):

	l2: l2-cache@500c0000 {

		compatible = "socionext,uniphier-system-cache";

		reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,

		      <0x506c0000 0x400>;

		cache-unified;

		cache-size = <0x200000>;

		cache-sets = <512>;

		cache-line-size = <128>;

		cache-level = <2>;

		next-level-cache = <&l3>;

	};



	l3: l3-cache@500c8000 {

		compatible = "socionext,uniphier-system-cache";

		reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,

		      <0x506c8000 0x400>;

		cache-unified;

		cache-size = <0x400000>;

		cache-sets = <512>;

		cache-line-size = <256>;

		cache-level = <3>;

	};

MAINTAINERS

+2 −0
Original line number Diff line number Diff line
@@ -1606,7 +1606,9 @@ M: Masahiro Yamada <yamada.masahiro@socionext.com> 
L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

S:	Maintained

F:	arch/arm/boot/dts/uniphier*

F:	arch/arm/include/asm/hardware/cache-uniphier.h

F:	arch/arm/mach-uniphier/

F:	arch/arm/mm/cache-uniphier.c

F:	drivers/pinctrl/uniphier/

F:	drivers/tty/serial/8250/8250_uniphier.c

N:	uniphier

arch/arm/include/asm/hardware/cache-uniphier.h

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/*

 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef __CACHE_UNIPHIER_H

#define __CACHE_UNIPHIER_H



#include <linux/types.h>



#ifdef CONFIG_CACHE_UNIPHIER

int uniphier_cache_init(void);

int uniphier_cache_l2_is_enabled(void);

void uniphier_cache_l2_touch_range(unsigned long start, unsigned long end);

void uniphier_cache_l2_set_locked_ways(u32 way_mask);

#else

static inline int uniphier_cache_init(void)

{

	return -ENODEV;

}



static inline int uniphier_cache_l2_is_enabled(void)

{

	return 0;

}



static inline void uniphier_cache_l2_touch_range(unsigned long start,

						 unsigned long end)

{

}



static inline void uniphier_cache_l2_set_locked_ways(u32 way_mask)

{

}

#endif



#endif /* __CACHE_UNIPHIER_H */

arch/arm/kernel/irq.c

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@@ -39,6 +39,7 @@ 
#include <linux/export.h>



#include <asm/hardware/cache-l2x0.h>

#include <asm/hardware/cache-uniphier.h>

#include <asm/outercache.h>

#include <asm/exception.h>

#include <asm/mach/arch.h>
@@ -97,6 +98,8 @@ void __init init_IRQ(void) 
		if (ret)

			pr_err("L2C: failed to init: %d\n", ret);

	}



	uniphier_cache_init();

}



#ifdef CONFIG_MULTI_IRQ_HANDLER

arch/arm/mm/Kconfig

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@@ -986,6 +986,16 @@ config CACHE_TAUROS2 
	  This option enables the Tauros2 L2 cache controller (as

	  found on PJ1/PJ4).



config CACHE_UNIPHIER

	bool "Enable the UniPhier outer cache controller"

	depends on ARCH_UNIPHIER

	default y

	select OUTER_CACHE

	select OUTER_CACHE_SYNC

	help

	  This option enables the UniPhier outer cache (system cache)

	  controller.



config CACHE_XSC3L2

	bool "Enable the L2 cache on XScale3"

	depends on CPU_XSC3

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