Commit e7cea790 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2020-05-15' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "As mentioned last week an i915 PR came in late, but I left it, so the
  i915 bits of this cover 2 weeks, which is why it's likely a bit larger
  than usual.

  Otherwise it's mostly amdgpu fixes, one tegra fix, one meson fix.

  i915:
   - Handle idling during i915_gem_evict_something busy loops (Chris)
   - Mark current submissions with a weak-dependency (Chris)
   - Propagate error from completed fences (Chris)
   - Fixes on execlist to avoid GPU hang situation (Chris)
   - Fixes couple deadlocks (Chris)
   - Timeslice preemption fixes (Chris)
   - Fix Display Port interrupt handling on Tiger Lake (Imre)
   - Reduce debug noise around Frame Buffer Compression (Peter)
   - Fix logic around IPC W/a for Coffee Lake and Kaby Lake (Sultan)
   - Avoid dereferencing a dead context (Chris)

  tegra:
   - tegra120/4 smmu fixes

  amdgpu:
   - Clockgating fixes
   - Fix fbdev with scatter/gather display
   - S4 fix for navi
   - Soft recovery for gfx10
   - Freesync fixes
   - Atomic check cursor fix
   - Add a gfxoff quirk
   - MST fix

  amdkfd:
   - Fix GEM reference counting

  meson:
   - error code propogation fix"

* tag 'drm-fixes-2020-05-15' of git://anongit.freedesktop.org/drm/drm: (29 commits)
  drm/i915: Handle idling during i915_gem_evict_something busy loops
  drm/meson: pm resume add return errno branch
  drm/amd/amdgpu: Update update_config() logic
  drm/amd/amdgpu: add raven1 part to the gfxoff quirk list
  drm/i915: Mark concurrent submissions with a weak-dependency
  drm/i915: Propagate error from completed fences
  drm/i915/gvt: Fix kernel oops for 3-level ppgtt guest
  drm/i915/gvt: Init DPLL/DDI vreg for virtual display instead of inheritance.
  drm/amd/display: add basic atomic check for cursor plane
  drm/amd/display: Fix vblank and pageflip event handling for FreeSync
  drm/amdgpu: implement soft_recovery for gfx10
  drm/amdgpu: enable hibernate support on Navi1X
  drm/amdgpu: Use GEM obj reference for KFD BOs
  drm/amdgpu: force fbdev into vram
  drm/amd/powerplay: perform PG ungate prior to CG ungate
  drm/amdgpu: drop unnecessary cancel_delayed_work_sync on PG ungate
  drm/amdgpu: disable MGCG/MGLS also on gfx CG ungate
  drm/i915/execlists: Track inflight CCID
  drm/i915/execlists: Avoid reusing the same logical CCID
  drm/i915/gem: Remove object_is_locked assertion from unpin_from_display_plane
  ...
parents 1ae7efb3 1d2a1eb1

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+1 −0
Original line number Diff line number Diff line
@@ -945,6 +945,7 @@ struct amdgpu_device { 


	/* s3/s4 mask */

	bool                            in_suspend;

	bool				in_hibernate;



	/* record last mm index being written through WREG32*/

	unsigned long last_mm_index;

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

+3 −2
Original line number Diff line number Diff line
@@ -1343,7 +1343,7 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( 
	}



	/* Free the BO*/

	amdgpu_bo_unref(&mem->bo);

	drm_gem_object_put_unlocked(&mem->bo->tbo.base);

	mutex_destroy(&mem->lock);

	kfree(mem);
@@ -1688,7 +1688,8 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd, 
		| KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE

		| KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE;



	(*mem)->bo = amdgpu_bo_ref(bo);

	drm_gem_object_get(&bo->tbo.base);

	(*mem)->bo = bo;

	(*mem)->va = va;

	(*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?

		AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT;

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+2 −0
Original line number Diff line number Diff line
@@ -1181,7 +1181,9 @@ static int amdgpu_pmops_freeze(struct device *dev) 
	struct amdgpu_device *adev = drm_dev->dev_private;

	int r;



	adev->in_hibernate = true;

	r = amdgpu_device_suspend(drm_dev, true);

	adev->in_hibernate = false;

	if (r)

		return r;

	return amdgpu_asic_reset(adev);

drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c

+1 −2
Original line number Diff line number Diff line
@@ -133,8 +133,7 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, 
	u32 cpp;

	u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |

			       AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS     |

			       AMDGPU_GEM_CREATE_VRAM_CLEARED 	     |

			       AMDGPU_GEM_CREATE_CPU_GTT_USWC;

			       AMDGPU_GEM_CREATE_VRAM_CLEARED;



	info = drm_get_format_info(adev->ddev, mode_cmd);

	cpp = info->cpp[0];

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+16 −6
Original line number Diff line number Diff line
@@ -4273,7 +4273,7 @@ static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 
		/* ===  CGCG /CGLS for GFX 3D Only === */

		gfx_v10_0_update_3d_clock_gating(adev, enable);

		/* ===  MGCG + MGLS === */

		/* gfx_v10_0_update_medium_grain_clock_gating(adev, enable); */

		gfx_v10_0_update_medium_grain_clock_gating(adev, enable);

	}



	if (adev->cg_flags &
@@ -4353,11 +4353,7 @@ static int gfx_v10_0_set_powergating_state(void *handle, 
	switch (adev->asic_type) {

	case CHIP_NAVI10:

	case CHIP_NAVI14:

		if (!enable) {

			amdgpu_gfx_off_ctrl(adev, false);

			cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);

		} else

			amdgpu_gfx_off_ctrl(adev, true);

		amdgpu_gfx_off_ctrl(adev, enable);

		break;

	default:

		break;
@@ -4918,6 +4914,19 @@ static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 
							   ref, mask);

}



static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,

					 unsigned vmid)

{

	struct amdgpu_device *adev = ring->adev;

	uint32_t value = 0;



	value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);

	value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);

	value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);

	value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);

	WREG32_SOC15(GC, 0, mmSQ_CMD, value);

}



static void

gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,

				      uint32_t me, uint32_t pipe,
@@ -5309,6 +5318,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 
	.emit_wreg = gfx_v10_0_ring_emit_wreg,

	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,

	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,

	.soft_recovery = gfx_v10_0_ring_soft_recovery,

};



static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {

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