Merge tag 'media/v5.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media

			the VE

 - interrupts:		the interrupt associated with the VE on this platform

Optional properties:

 - memory-region:

	phandle to a memory region to allocate from, as defined in

	Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt

Example:

video-engine@1e700000 {

    clock-names = "vclk", "eclk";

    resets = <&syscon ASPEED_RESET_VIDEO>;

    interrupts = <7>;

    memory-region = <&video_engine_memory>;

};

			- "allwinner,sun8i-h3-video-engine"

			- "allwinner,sun50i-a64-video-engine"

			- "allwinner,sun50i-h5-video-engine"

			- "allwinner,sun50i-h6-video-engine"

- reg			: register base and length of VE;

- clocks		: list of clock specifiers, corresponding to entries in

			  the clock-names property;

STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge

MIPID02 has two CSI-2 input ports, only one of those ports can be active at a

time. Active port input stream will be de-serialized and its content outputted

through PARALLEL output port.

CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second

input port is a single lane 800Mbps. Both ports support clock and data lane

polarity swap. First port also supports data lane swap.

PARALLEL output port has a maximum width of 12 bits.

Supported formats are RAW6, RAW7, RAW8, RAW10, RAW12, RGB565, RGB888, RGB444,

YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.

Required Properties:

- compatible: shall be "st,st-mipid02"

- clocks: reference to the xclk input clock.

- clock-names: shall be "xclk".

- VDDE-supply: sensor digital IO supply. Must be 1.8 volts.

- VDDIN-supply: sensor internal regulator supply. Must be 1.8 volts.

Optional Properties:

- reset-gpios: reference to the GPIO connected to the xsdn pin, if any.

	       This is an active low signal to the mipid02.

Required subnodes:

  - ports: A ports node with one port child node per device input and output

	   port, in accordance with the video interface bindings defined in

	   Documentation/devicetree/bindings/media/video-interfaces.txt. The

	   port nodes are numbered as follows:

	   Port Description

	   -----------------------------

	   0    CSI-2 first input port

	   1    CSI-2 second input port

	   2    PARALLEL output

Endpoint node required property for CSI-2 connection is:

- data-lanes: shall be <1> for Port 1. for Port 0 dual-lane operation shall be

<1 2> or <2 1>. For Port 0 single-lane operation shall be <1> or <2>.

Endpoint node optional property for CSI-2 connection is:

- lane-polarities: any lane can be inverted or not.

Endpoint node required property for PARALLEL connection is:

- bus-width: shall be set to <6>, <7>, <8>, <10> or <12>.

Endpoint node optional properties for PARALLEL connection are:

- hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH respectively.

LOW being the default.

- vsync-active: active state of the VSYNC signal, 0/1 for LOW/HIGH respectively.

LOW being the default.

Example:

mipid02: csi2rx@14 {

	compatible = "st,st-mipid02";

	reg = <0x14>;

	status = "okay";

	clocks = <&clk_ext_camera_12>;

	clock-names = "xclk";

	VDDE-supply = <&vdd>;

	VDDIN-supply = <&vdd>;

	ports {

		#address-cells = <1>;

		#size-cells = <0>;

		port@0 {

			reg = <0>;

			ep0: endpoint {

				data-lanes = <1 2>;

				remote-endpoint = <&mipi_csi2_in>;

			};

		};

		port@2 {

			reg = <2>;

			ep2: endpoint {

				bus-width = <8>;

				hsync-active = <0>;

				vsync-active = <0>;

				remote-endpoint = <&parallel_out>;

			};

		};

	};

};

to handle communication between HDMI connected devices over the CEC bus.

Required properties:

  - compatible : value should be following

  - compatible : value should be following depending on the SoC :

	For GXBB, GXL, GXM and G12A (AO_CEC_A module) :

	"amlogic,meson-gx-ao-cec"

	For G12A (AO_CEC_B module) :

	"amlogic,meson-g12a-ao-cec"

  - reg : Physical base address of the IP registers and length of memory

	  mapped region.

  - interrupts : AO-CEC interrupt number to the CPU.

  - clocks : from common clock binding: handle to AO-CEC clock.

  - clock-names : from common clock binding: must contain "core",

  - clock-names : from common clock binding, must contain :

		For GXBB, GXL, GXM and G12A (AO_CEC_A module) :

		- "core"

		For G12A (AO_CEC_B module) :

		- "oscin"

		corresponding to entry in the clocks property.

  - hdmi-phandle: phandle to the HDMI controller

Renesas R-Car Image Renderer (Distortion Correction Engine)

-----------------------------------------------------------

The image renderer, or the distortion correction engine, is a drawing processor

with a simple instruction system capable of referencing video capture data or

data in an external memory as 2D texture data and performing texture mapping

and drawing with respect to any shape that is split into triangular objects.

Required properties:

- compatible: "renesas,<soctype>-imr-lx4", "renesas,imr-lx4" as a fallback for

  the image renderer light extended 4 (IMR-LX4) found in the R-Car gen3 SoCs,

  where the examples with <soctype> are:

  - "renesas,r8a7795-imr-lx4" for R-Car H3,

  - "renesas,r8a7796-imr-lx4" for R-Car M3-W.

- reg: offset and length of the register block;

- interrupts: single interrupt specifier;

- clocks: single clock phandle/specifier pair;

- power-domains: power domain phandle/specifier pair;

- resets: reset phandle/specifier pair.

Example:

	imr-lx4@fe860000 {

		compatible = "renesas,r8a7795-imr-lx4", "renesas,imr-lx4";

		reg = <0 0xfe860000 0 0x2000>;

		interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cpg CPG_MOD 823>;

		power-domains = <&sysc R8A7795_PD_A3VC>;

		resets = <&cpg 823>;

	};