drm/amdgpu: Export setup_vm_pt_regs() logic for mmhub 2.0 (e7956997) · Commits · 戴 / test

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

+12 −7

Original line number	Diff line number	Diff line
		@@ -31,20 +31,25 @@

		#include "soc15_common.h"

		static void mmhub_v2_0_init_gart_pt_regs(struct amdgpu_device *adev)
		void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
		uint64_t page_table_base)
		{
		uint64_t value = amdgpu_gmc_pd_addr(adev->gart.bo);
		/* two registers distance between mmMMVM_CONTEXT0_* to mmMMVM_CONTEXT1_* */
		int offset = mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
		- mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;

		WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
		lower_32_bits(value));
		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
		offset * vmid, lower_32_bits(page_table_base));

		WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
		upper_32_bits(value));
		WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
		offset * vmid, upper_32_bits(page_table_base));
		}

		static void mmhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev)
		{
		mmhub_v2_0_init_gart_pt_regs(adev);
		uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);

		mmhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base);

		WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
		(u32)(adev->gmc.gart_start >> 12));

+2 −0

Original line number	Diff line number	Diff line
		@@ -31,5 +31,7 @@ void mmhub_v2_0_init(struct amdgpu_device *adev);
		int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
		enum amd_clockgating_state state);
		void mmhub_v2_0_get_clockgating(struct amdgpu_device adev, u32 flags);
		void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
		uint64_t page_table_base);

		#endif