Unverified Commit e78adcfe authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Maxime Ripard
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ARM: dts: sun9i: Add GMAC clock node



The A80 has the same DWMAC hardware as on earlier Allwinner SoCs. The
accompanying GMAC clock register has been moved into the "System
Control" area.

Add a clock node for it.

Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
parent b3e1f4be
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+31 −0
Original line number Diff line number Diff line
@@ -183,6 +183,37 @@
			clock-output-names = "osc32k";
		};

		/*
		 * The following two are dummy clocks, placeholders
		 * used in the gmac_tx clock. The gmac driver will
		 * choose one parent depending on the PHY interface
		 * mode, using clk_set_rate auto-reparenting.
		 *
		 * The actual TX clock rate is not controlled by the
		 * gmac_tx clock.
		 */
		mii_phy_tx_clk: mii_phy_tx_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <25000000>;
			clock-output-names = "mii_phy_tx";
		};

		gmac_int_tx_clk: gmac_int_tx_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <125000000>;
			clock-output-names = "gmac_int_tx";
		};

		gmac_tx_clk: clk@800030 {
			#clock-cells = <0>;
			compatible = "allwinner,sun7i-a20-gmac-clk";
			reg = <0x00800030 0x4>;
			clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
			clock-output-names = "gmac_tx";
		};

		cpus_clk: clk@8001410 {
			compatible = "allwinner,sun9i-a80-cpus-clk";
			reg = <0x08001410 0x4>;