Commit e777f8c8 authored by Linus Walleij's avatar Linus Walleij
Browse files

Merge tag 'renesas-pinctrl-for-v5.10-tag1' of... 

Merge tag 'renesas-pinctrl-for-v5.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: renesas: Updates for v5.10

  - Add CAN and USB1 PWEN pin groups on R-Car H2 and RZ/G1,
  - Three more conversion of DT bindings to json-schema,
  - Group all Renesas pinctrl drivers and improve visual Kconfig
    structure,
  - Rename drivers/pinctrl/sh-pfc to drivers/pinctrl/renesas,
  - Minor fixes and improvements.
parents 84f28fc3 540d9757

Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt

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* Renesas Pin Function Controller (GPIO and Pin Mux/Config)



The Pin Function Controller (PFC) is a Pin Mux/Config controller. On SH73A0,

R8A73A4 and R8A7740 it also acts as a GPIO controller.





Pin Control

-----------



Required Properties:



  - compatible: should be one of the following.

    - "renesas,pfc-emev2": for EMEV2 (EMMA Mobile EV2) compatible pin-controller.

    - "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller.

    - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.

    - "renesas,pfc-r8a7742": for R8A7742 (RZ/G1H) compatible pin-controller.

    - "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller.

    - "renesas,pfc-r8a7744": for R8A7744 (RZ/G1N) compatible pin-controller.

    - "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller.

    - "renesas,pfc-r8a77470": for R8A77470 (RZ/G1C) compatible pin-controller.

    - "renesas,pfc-r8a774a1": for R8A774A1 (RZ/G2M) compatible pin-controller.

    - "renesas,pfc-r8a774b1": for R8A774B1 (RZ/G2N) compatible pin-controller.

    - "renesas,pfc-r8a774c0": for R8A774C0 (RZ/G2E) compatible pin-controller.

    - "renesas,pfc-r8a774e1": for R8A774E1 (RZ/G2H) compatible pin-controller.

    - "renesas,pfc-r8a7778": for R8A7778 (R-Car M1) compatible pin-controller.

    - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.

    - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.

    - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller.

    - "renesas,pfc-r8a7792": for R8A7792 (R-Car V2H) compatible pin-controller.

    - "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller.

    - "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.

    - "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller.

    - "renesas,pfc-r8a7796": for R8A77960 (R-Car M3-W) compatible pin-controller.

    - "renesas,pfc-r8a77961": for R8A77961 (R-Car M3-W+) compatible pin-controller.

    - "renesas,pfc-r8a77965": for R8A77965 (R-Car M3-N) compatible pin-controller.

    - "renesas,pfc-r8a77970": for R8A77970 (R-Car V3M) compatible pin-controller.

    - "renesas,pfc-r8a77980": for R8A77980 (R-Car V3H) compatible pin-controller.

    - "renesas,pfc-r8a77990": for R8A77990 (R-Car E3) compatible pin-controller.

    - "renesas,pfc-r8a77995": for R8A77995 (R-Car D3) compatible pin-controller.

    - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.



  - reg: Base address and length of each memory resource used by the pin

    controller hardware module.



Optional properties:



  - #gpio-range-cells: Mandatory when the PFC doesn't handle GPIO, forbidden

    otherwise. Should be 3.



  - interrupts-extended: Specify the interrupts associated with external

    IRQ pins. This property is mandatory when the PFC handles GPIOs and

    forbidden otherwise. When specified, it must contain one interrupt per

    external IRQ, sorted by external IRQ number.



The PFC node also acts as a container for pin configuration nodes. Please refer

to pinctrl-bindings.txt in this directory for the definition of the term "pin

configuration node" and for the common pinctrl bindings used by client devices.



Each pin configuration node represents a desired configuration for a pin, a

pin group, or a list of pins or pin groups. The configuration can include the

function to select on those pin(s) and pin configuration parameters (such as

pull-up and pull-down).



Pin configuration nodes contain pin configuration properties, either directly

or grouped in child subnodes. Both pin muxing and configuration parameters can

be grouped in that way and referenced as a single pin configuration node by

client devices.



A configuration node or subnode must reference at least one pin (through the

pins or pin groups properties) and contain at least a function or one

configuration parameter. When the function is present only pin groups can be

used to reference pins.



All pin configuration nodes and subnodes names are ignored. All of those nodes

are parsed through phandles and processed purely based on their content.



Pin Configuration Node Properties:



- pins : An array of strings, each string containing the name of a pin.

- groups : An array of strings, each string containing the name of a pin

  group.



- function: A string containing the name of the function to mux to the pin

  group(s) specified by the groups property.



  Valid values for pin, group and function names can be found in the group and

  function arrays of the PFC data file corresponding to the SoC

  (drivers/pinctrl/sh-pfc/pfc-*.c)



The pin configuration parameters use the generic pinconf bindings defined in

pinctrl-bindings.txt in this directory. The supported parameters are

bias-disable, bias-pull-up, bias-pull-down, drive-strength and power-source. For

pins that have a configurable I/O voltage, the power-source value should be the

nominal I/O voltage in millivolts.





GPIO

----



On SH73A0, R8A73A4 and R8A7740 the PFC node is also a GPIO controller node.



Required Properties:



  - gpio-controller: Marks the device node as a gpio controller.



  - #gpio-cells: Should be 2. The first cell is the GPIO number and the second

    cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the

    GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.



The syntax of the gpio specifier used by client nodes should be the following

with values derived from the SoC user manual.



  <[phandle of the gpio controller node]

   [pin number within the gpio controller]

   [flags]>



On other mach-shmobile platforms GPIO is handled by the gpio-rcar driver.

Please refer to Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml

for documentation of the GPIO device tree bindings on those platforms.





Examples

--------



Example 1: SH73A0 (SH-Mobile AG5) pin controller node



	pfc: pin-controller@e6050000 {

		compatible = "renesas,pfc-sh73a0";

		reg = <0xe6050000 0x8000>,

		      <0xe605801c 0x1c>;

		gpio-controller;

		#gpio-cells = <2>;

		interrupts-extended =

			<&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,

			<&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,

			<&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,

			<&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,

			<&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,

			<&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,

			<&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,

			<&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;

	};



Example 2: A GPIO LED node that references a GPIO



	#include <dt-bindings/gpio/gpio.h>



	leds {

		compatible = "gpio-leds";

		led1 {

			gpios = <&pfc 20 GPIO_ACTIVE_LOW>;

		};

	};



Example 3: KZM-A9-GT (SH-Mobile AG5) default pin state hog and pin control maps

           for the MMCIF and SCIFA4 devices



	&pfc {

		pinctrl-0 = <&scifa4_pins>;

		pinctrl-names = "default";



		mmcif_pins: mmcif {

			mux {

				groups = "mmc0_data8_0", "mmc0_ctrl_0";

				function = "mmc0";

			};

			cfg {

				groups = "mmc0_data8_0";

				pins = "PORT279";

				bias-pull-up;

			};

		};



		scifa4_pins: scifa4 {

			groups = "scifa4_data", "scifa4_ctrl";

			function = "scifa4";

		};

	};



Example 4: KZM-A9-GT (SH-Mobile AG5) default pin state for the MMCIF device



	&mmcif {

		pinctrl-0 = <&mmcif_pins>;

		pinctrl-names = "default";



		bus-width = <8>;

		vmmc-supply = <&reg_1p8v>;

	};

Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/renesas,pfc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas Pin Function Controller (GPIO and Pin Mux/Config)



maintainers:

  - Geert Uytterhoeven <geert+renesas@glider.be>



description:

  The Pin Function Controller (PFC) is a Pin Mux/Config controller.

  On SH/R-Mobile SoCs it also acts as a GPIO controller.



properties:

  compatible:

    enum:

      - renesas,pfc-emev2       # EMMA Mobile EV2

      - renesas,pfc-r8a73a4     # R-Mobile APE6

      - renesas,pfc-r8a7740     # R-Mobile A1

      - renesas,pfc-r8a7742     # RZ/G1H

      - renesas,pfc-r8a7743     # RZ/G1M

      - renesas,pfc-r8a7744     # RZ/G1N

      - renesas,pfc-r8a7745     # RZ/G1E

      - renesas,pfc-r8a77470    # RZ/G1C

      - renesas,pfc-r8a774a1    # RZ/G2M

      - renesas,pfc-r8a774b1    # RZ/G2N

      - renesas,pfc-r8a774c0    # RZ/G2E

      - renesas,pfc-r8a774e1    # RZ/G2H

      - renesas,pfc-r8a7778     # R-Car M1

      - renesas,pfc-r8a7779     # R-Car H1

      - renesas,pfc-r8a7790     # R-Car H2

      - renesas,pfc-r8a7791     # R-Car M2-W

      - renesas,pfc-r8a7792     # R-Car V2H

      - renesas,pfc-r8a7793     # R-Car M2-N

      - renesas,pfc-r8a7794     # R-Car E2

      - renesas,pfc-r8a7795     # R-Car H3

      - renesas,pfc-r8a7796     # R-Car M3-W

      - renesas,pfc-r8a77961    # R-Car M3-W+

      - renesas,pfc-r8a77965    # R-Car M3-N

      - renesas,pfc-r8a77970    # R-Car V3M

      - renesas,pfc-r8a77980    # R-Car V3H

      - renesas,pfc-r8a77990    # R-Car E3

      - renesas,pfc-r8a77995    # R-Car D3

      - renesas,pfc-sh73a0      # SH-Mobile AG5



  reg:

    minItems: 1

    maxItems: 2



  gpio-controller: true



  '#gpio-cells':

    const: 2



  gpio-ranges:

    minItems: 1

    maxItems: 16



  interrupts-extended:

    minItems: 32

    maxItems: 64

    description:

      Specify the interrupts associated with external IRQ pins on SoCs where

      the PFC acts as a GPIO controller.  It must contain one interrupt per

      external IRQ, sorted by external IRQ number.



  power-domains:

    maxItems: 1



required:

  - compatible

  - reg



if:

  properties:

    compatible:

      items:

        enum:

          - renesas,pfc-r8a73a4

          - renesas,pfc-r8a7740

          - renesas,pfc-sh73a0

then:

  required:

    - interrupts-extended

    - gpio-controller

    - '#gpio-cells'

    - gpio-ranges

    - power-domains



additionalProperties:

  anyOf:

    - type: object

      allOf:

        - $ref: pincfg-node.yaml#

        - $ref: pinmux-node.yaml#



      description:

        Pin controller client devices use pin configuration subnodes (children

        and grandchildren) for desired pin configuration.

        Client device subnodes use below standard properties.



      properties:

        phandle: true

        function: true

        groups: true

        pins: true

        bias-disable: true

        bias-pull-down: true

        bias-pull-up: true

        drive-strength:

          enum: [ 3, 6, 9, 12, 15, 18, 21, 24 ] # Superset of supported values

        power-source:

          enum: [ 1800, 3300 ]

        gpio-hog: true

        gpios: true

        input: true

        output-high: true

        output-low: true



      additionalProperties: false



    - type: object

      properties:

        phandle: true



      additionalProperties:

        $ref: "#/additionalProperties/anyOf/0"



examples:

  - |

    pfc: pinctrl@e6050000 {

            compatible = "renesas,pfc-r8a7740";

            reg = <0xe6050000 0x8000>,

                  <0xe605800c 0x20>;

            gpio-controller;

            #gpio-cells = <2>;

            gpio-ranges = <&pfc 0 0 212>;

            interrupts-extended =

                <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,

                <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,

                <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,

                <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,

                <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,

                <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,

                <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,

                <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;

            power-domains = <&pd_c5>;



            lcd0_mux {

                    /* DBGMD/LCDC0/FSIA MUX */

                    gpio-hog;

                    gpios = <176 0>;

                    output-high;

            };

    };



  - |

    pinctrl@e6060000 {

            compatible = "renesas,pfc-r8a7795";

            reg = <0xe6060000 0x50c>;



            avb_pins: avb {

                    mux {

                            groups = "avb_link", "avb_mdio", "avb_mii";

                            function = "avb";

                    };



                    pins_mdio {

                            groups = "avb_mdio";

                            drive-strength = <24>;

                    };



                    pins_mii_tx {

                            pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC",

                                   "PIN_AVB_TD0", "PIN_AVB_TD1", "PIN_AVB_TD2",

                                   "PIN_AVB_TD3";

                            drive-strength = <12>;

                    };

            };



            keys_pins: keys {

                    pins = "GP_5_17", "GP_5_20", "GP_5_22", "GP_2_1";

                    bias-pull-up;

            };



            sdhi0_pins: sd0 {

                    groups = "sdhi0_data4", "sdhi0_ctrl";

                    function = "sdhi0";

                    power-source = <3300>;

            };

    };

Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt

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Renesas RZ/A1 combined Pin and GPIO controller



The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO controller,

named "Ports" in the hardware reference manual.

Pin multiplexing and GPIO configuration is performed on a per-pin basis

writing configuration values to per-port register sets.

Each "port" features up to 16 pins, each of them configurable for GPIO

function (port mode) or in alternate function mode.

Up to 8 different alternate function modes exist for each single pin.



Pin controller node

-------------------



Required properties:

  - compatible: should be:

    - "renesas,r7s72100-ports": for RZ/A1H

    - "renesas,r7s72101-ports", "renesas,r7s72100-ports": for RZ/A1M

    - "renesas,r7s72102-ports": for RZ/A1L



  - reg

    address base and length of the memory area where the pin controller

    hardware is mapped to.



Example:

Pin controller node for RZ/A1H SoC (r7s72100)



pinctrl: pin-controller@fcfe3000 {

	compatible = "renesas,r7s72100-ports";



	reg = <0xfcfe3000 0x4230>;

};



Sub-nodes

---------



The child nodes of the pin controller node describe a pin multiplexing

function or a GPIO controller alternatively.



- Pin multiplexing sub-nodes:

  A pin multiplexing sub-node describes how to configure a set of

  (or a single) pin in some desired alternate function mode.

  A single sub-node may define several pin configurations.

  A few alternate function require special pin configuration flags to be

  supplied along with the alternate function configuration number.

  The hardware reference manual specifies when a pin function requires

  "software IO driven" mode to be specified. To do so use the generic

  properties from the <include/linux/pinctrl/pinconf_generic.h> header file

  to instruct the pin controller to perform the desired pin configuration

  operation.

  Please refer to pinctrl-bindings.txt to get to know more on generic

  pin properties usage.



  The allowed generic formats for a pin multiplexing sub-node are the

  following ones:



  node-1 {

      pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;

      GENERIC_PINCONFIG;

  };



  node-2 {

      sub-node-1 {

          pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;

          GENERIC_PINCONFIG;

      };



      sub-node-2 {

          pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;

          GENERIC_PINCONFIG;

      };



      ...



      sub-node-n {

          pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;

          GENERIC_PINCONFIG;

      };

  };



  Use the second format when pins part of the same logical group need to have

  different generic pin configuration flags applied.



  Client sub-nodes shall refer to pin multiplexing sub-nodes using the phandle

  of the most external one.



  Eg.



  client-1 {

      ...

      pinctrl-0 = <&node-1>;

      ...

  };



  client-2 {

      ...

      pinctrl-0 = <&node-2>;

      ...

  };



  Required properties:

    - pinmux:

      integer array representing pin number and pin multiplexing configuration.

      When a pin has to be configured in alternate function mode, use this

      property to identify the pin by its global index, and provide its

      alternate function configuration number along with it.

      When multiple pins are required to be configured as part of the same

      alternate function they shall be specified as members of the same

      argument list of a single "pinmux" property.

      Helper macros to ease assembling the pin index from its position

      (port where it sits on and pin number) and alternate function identifier

      are provided by the pin controller header file at:

      <include/dt-bindings/pinctrl/r7s72100-pinctrl.h>

      Integers values in "pinmux" argument list are assembled as:

      ((PORT * 16 + PIN) | MUX_FUNC << 16)



  Optional generic properties:

    - input-enable:

      enable input bufer for pins requiring software driven IO input

      operations.

    - output-high:

      enable output buffer for pins requiring software driven IO output

      operations. output-low can be used alternatively, as line value is

      ignored by the driver.



  The hardware reference manual specifies when a pin has to be configured to

  work in bi-directional mode and when the IO direction has to be specified

  by software. Bi-directional pins are managed by the pin controller driver

  internally, while software driven IO direction has to be explicitly

  selected when multiple options are available.



  Example:

  A serial communication interface with a TX output pin and an RX input pin.



  &pinctrl {

	scif2_pins: serial2 {

		pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>;

	};

  };



  Pin #0 on port #3 is configured as alternate function #6.

  Pin #2 on port #3 is configured as alternate function #4.



  Example 2:

  I2c master: both SDA and SCL pins need bi-directional operations



  &pinctrl {

	i2c2_pins: i2c2 {

		pinmux = <RZA1_PINMUX(1, 4, 1)>, <RZA1_PINMUX(1, 5, 1)>;

	};

  };



  Pin #4 on port #1 is configured as alternate function #1.

  Pin #5 on port #1 is configured as alternate function #1.

  Both need to work in bi-directional mode, the driver manages this internally.



  Example 3:

  Multi-function timer input and output compare pins.

  Configure TIOC0A as software driven input and TIOC0B as software driven

  output.



  &pinctrl {

	tioc0_pins: tioc0 {

		tioc0_input_pins {

			pinumx = <RZA1_PINMUX(4, 0, 2)>;

			input-enable;

		};



		tioc0_output_pins {

			pinmux = <RZA1_PINMUX(4, 1, 1)>;

			output-enable;

		};

	};

  };



  &tioc0 {

	...

	pinctrl-0 = <&tioc0_pins>;

	...

  };



  Pin #0 on port #4 is configured as alternate function #2 with IO direction

  specified by software as input.

  Pin #1 on port #4 is configured as alternate function #1 with IO direction

  specified by software as output.



- GPIO controller sub-nodes:

  Each port of the r7s72100 pin controller hardware is itself a GPIO controller.

  Different SoCs have different numbers of available pins per port, but

  generally speaking, each of them can be configured in GPIO ("port") mode

  on this hardware.

  Describe GPIO controllers using sub-nodes with the following properties.



  Required properties:

    - gpio-controller

      empty property as defined by the GPIO bindings documentation.

    - #gpio-cells

      number of cells required to identify and configure a GPIO.

      Shall be 2.

    - gpio-ranges

      Describes a GPIO controller specifying its specific pin base, the pin

      base in the global pin numbering space, and the number of controlled

      pins, as defined by the GPIO bindings documentation. Refer to

      Documentation/devicetree/bindings/gpio/gpio.txt file for a more detailed

      description.



  Example:

  A GPIO controller node, controlling 16 pins indexed from 0.

  The GPIO controller base in the global pin indexing space is pin 48, thus

  pins [0 - 15] on this controller map to pins [48 - 63] in the global pin

  indexing space.



  port3: gpio-3 {

	gpio-controller;

	#gpio-cells = <2>;

	gpio-ranges = <&pinctrl 0 48 16>;

  };



  A device node willing to use pins controlled by this GPIO controller, shall

  refer to it as follows:



  led1 {

	gpios = <&port3 10 GPIO_ACTIVE_LOW>;

  };

Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml

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Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml

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@@ -84,7 +84,7 @@ additionalProperties: false 
examples:

  - |

    #include <dt-bindings/pinctrl/r7s9210-pinctrl.h>

    pinctrl: pin-controller@fcffe000 {

    pinctrl: pinctrl@fcffe000 {

            compatible = "renesas,r7s9210-pinctrl";

            reg = <0xfcffe000 0x1000>;

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