Commit e76e5682 authored by Jae Hyun Yoo's avatar Jae Hyun Yoo Committed by Stephen Boyd
Browse files

clk:aspeed: Fix reset bits for PCI/VGA and PECI 



This commit fixes incorrect setting of reset bits for PCI/VGA and
PECI modules.

1. Reset bit for PCI/VGA is 8.
2. PECI reset bit is missing so added bit 10 as its reset bit.

Signed-off-by: default avatarJae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Fixes: 15ed8ce5 ("clk: aspeed: Register gated clocks")
Cc: stable <stable@vger.kernel.org>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent dcb899c4

drivers/clk/clk-aspeed.c

+2 −2
Original line number Diff line number Diff line
@@ -91,7 +91,7 @@ static const struct aspeed_gate_data aspeed_gates[] = { 
	[ASPEED_CLK_GATE_GCLK] =	{  1,  7, "gclk-gate",		NULL,	0 }, /* 2D engine */

	[ASPEED_CLK_GATE_MCLK] =	{  2, -1, "mclk-gate",		"mpll",	CLK_IS_CRITICAL }, /* SDRAM */

	[ASPEED_CLK_GATE_VCLK] =	{  3,  6, "vclk-gate",		NULL,	0 }, /* Video Capture */

	[ASPEED_CLK_GATE_BCLK] =	{  4, 10, "bclk-gate",		"bclk",	0 }, /* PCIe/PCI */

	[ASPEED_CLK_GATE_BCLK] =	{  4,  8, "bclk-gate",		"bclk",	0 }, /* PCIe/PCI */

	[ASPEED_CLK_GATE_DCLK] =	{  5, -1, "dclk-gate",		NULL,	0 }, /* DAC */

	[ASPEED_CLK_GATE_REFCLK] =	{  6, -1, "refclk-gate",	"clkin", CLK_IS_CRITICAL },

	[ASPEED_CLK_GATE_USBPORT2CLK] =	{  7,  3, "usb-port2-gate",	NULL,	0 }, /* USB2.0 Host port 2 */
@@ -301,7 +301,7 @@ static const u8 aspeed_resets[] = { 
	[ASPEED_RESET_JTAG_MASTER] = 22,

	[ASPEED_RESET_MIC]	= 18,

	[ASPEED_RESET_PWM]	=  9,

	[ASPEED_RESET_PCIVGA]	=  8,

	[ASPEED_RESET_PECI]	= 10,

	[ASPEED_RESET_I2C]	=  2,

	[ASPEED_RESET_AHB]	=  1,

include/dt-bindings/clock/aspeed-clock.h

+1 −1
Original line number Diff line number Diff line
@@ -45,7 +45,7 @@ 
#define ASPEED_RESET_JTAG_MASTER	3

#define ASPEED_RESET_MIC		4

#define ASPEED_RESET_PWM		5

#define ASPEED_RESET_PCIVGA		6

#define ASPEED_RESET_PECI		6

#define ASPEED_RESET_I2C		7

#define ASPEED_RESET_AHB		8

#define ASPEED_RESET_CRT1		9

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