Commit e76ab2cf authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Remove per-platform IIR HPD masking 



We no longer unmask all HPD irqs, so we can drop the ugly per-platform
HPD IIR masking. IMR will prevent unsupported bits from appearing in
IIR.

v2: Deal with DG1
    Include "HOTPLUG" in the mask names (Lucas)
v3: Fix typos in subject

Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201028213323.5423-17-ville.syrjala@linux.intel.com
parent 9a55a620

drivers/gpu/drm/i915/i915_irq.c

+2 −22
Original line number Diff line number Diff line
@@ -1895,30 +1895,10 @@ static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) 


static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)

{

	u32 ddi_hotplug_trigger, tc_hotplug_trigger;

	u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_HOTPLUG_MASK_ICP;

	u32 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_MASK_ICP;

	u32 pin_mask = 0, long_mask = 0;



	if (HAS_PCH_DG1(dev_priv)) {

		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_DG1;

		tc_hotplug_trigger = 0;

	} else if (HAS_PCH_TGP(dev_priv)) {

		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;

		tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;

	} else if (HAS_PCH_JSP(dev_priv)) {

		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;

		tc_hotplug_trigger = 0;

	} else if (HAS_PCH_MCC(dev_priv)) {

		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;

		tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1);

	} else {

		drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv),

			 "Unrecognized PCH type 0x%x\n",

			 INTEL_PCH_TYPE(dev_priv));



		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;

		tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;

	}



	if (ddi_hotplug_trigger) {

		u32 dig_hotplug_reg;

drivers/gpu/drm/i915/i915_reg.h

+3 −12
Original line number Diff line number Diff line
@@ -8352,25 +8352,16 @@ enum { 
#define SDE_GMBUS_ICP			(1 << 23)

#define SDE_TC_HOTPLUG_ICP(hpd_pin)	REG_BIT(24 + _HPD_PIN_TC(hpd_pin))

#define SDE_DDI_HOTPLUG_ICP(hpd_pin)	REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))

#define SDE_DDI_MASK_ICP		(SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \

					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))

#define SDE_TC_MASK_ICP			(SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \

					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \

					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \

					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))

#define SDE_DDI_MASK_TGP		(SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \

#define SDE_DDI_HOTPLUG_MASK_ICP	(SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \

					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \

					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \

					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))

#define SDE_TC_MASK_TGP			(SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \

#define SDE_TC_HOTPLUG_MASK_ICP		(SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \

					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \

					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \

					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \

					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \

					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))

#define SDE_DDI_MASK_DG1		(SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \

					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \

					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \

					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))



#define SDEISR  _MMIO(0xc4000)

#define SDEIMR  _MMIO(0xc4004)

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