ARM: dts: omap5.dtsi: add DSS nodes

			ti,hwmods = "sata";

		};

		dss: dss@58000000 {

			compatible = "ti,omap5-dss";

			reg = <0x58000000 0x80>;

			status = "disabled";

			ti,hwmods = "dss_core";

			clocks = <&dss_dss_clk>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;

			dispc@58001000 {

				compatible = "ti,omap5-dispc";

				reg = <0x58001000 0x1000>;

				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;

				ti,hwmods = "dss_dispc";

				clocks = <&dss_dss_clk>;

				clock-names = "fck";

			};

			dsi1: encoder@58004000 {

				compatible = "ti,omap5-dsi";

				reg = <0x58004000 0x200>,

				      <0x58004200 0x40>,

				      <0x58004300 0x40>;

				reg-names = "proto", "phy", "pll";

				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;

				status = "disabled";

				ti,hwmods = "dss_dsi1";

				clocks = <&dss_dss_clk>, <&dss_sys_clk>;

				clock-names = "fck", "sys_clk";

			};

			dsi2: encoder@58005000 {

				compatible = "ti,omap5-dsi";

				reg = <0x58009000 0x200>,

				      <0x58009200 0x40>,

				      <0x58009300 0x40>;

				reg-names = "proto", "phy", "pll";

				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;

				status = "disabled";

				ti,hwmods = "dss_dsi2";

				clocks = <&dss_dss_clk>, <&dss_sys_clk>;

				clock-names = "fck", "sys_clk";

			};

			hdmi: encoder@58060000 {

				compatible = "ti,omap5-hdmi";

				reg = <0x58040000 0x200>,

				      <0x58040200 0x80>,

				      <0x58040300 0x80>,

				      <0x58060000 0x19000>;

				reg-names = "wp", "pll", "phy", "core";

				interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;

				status = "disabled";

				ti,hwmods = "dss_hdmi";

				clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;

				clock-names = "fck", "sys_clk";

			};

		};

	};

};