Commit e7482c74 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'zynq-dt-for-4.3' of https://github.com/Xilinx/linux-xlnx into next/dt

arm: Xilinx Zynq dt patches for v4.3

- Add ECC for Synopsys MC
- Add OCM, pushbuttons to zc702

* tag 'zynq-dt-for-4.3' of https://github.com/Xilinx/linux-xlnx

:
  ARM: zynq: DT: Add zc702 pushbuttons to DT as gpio-keys
  ARM: zynq: DT: Add missing interrupt for L2 pl310
  Documentation: devicetree: Add ECC information to synopsys ddr controller
  ARM: dts: zynq: Add OCM node

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 75d84eed b76da4d8
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+4 −0
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Binding for Synopsys IntelliDDR Multi Protocol Memory Controller

This controller has an optional ECC support in half-bus width (16-bit)
configuration. The ECC controller corrects one bit error and detects
two bit errors.

Required properties:
 - compatible: Should be 'xlnx,zynq-ddrc-a05'
 - reg: Base address and size of the controllers memory area
+2 −1
Original line number Diff line number Diff line
@@ -57,7 +57,7 @@
		regulator-always-on;
	};

	amba {
	amba: amba {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
@@ -139,6 +139,7 @@
		L2: cache-controller@f8f02000 {
			compatible = "arm,pl310-cache";
			reg = <0xF8F02000 0x1000>;
			interrupts = <0 2 4>;
			arm,data-latency = <3 2 2>;
			arm,tag-latency = <2 2 2>;
			cache-unified;
+28 −0
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@@ -34,6 +34,27 @@
		stdout-path = "serial0:115200n8";
	};

	gpio-keys {
		compatible = "gpio-keys";
		#address-cells = <1>;
		#size-cells = <0>;
		autorepeat;
		sw14 {
			label = "sw14";
			gpios = <&gpio0 12 0>;
			linux,code = <108>; /* down */
			gpio-key,wakeup;
			autorepeat;
		};
		sw13 {
			label = "sw13";
			gpios = <&gpio0 14 0>;
			linux,code = <103>; /* up */
			gpio-key,wakeup;
			autorepeat;
		};
	};

	leds {
		compatible = "gpio-leds";

@@ -50,6 +71,13 @@
	};
};

&amba {
	ocm: sram@fffc0000 {
		compatible = "mmio-sram";
		reg = <0xfffc0000 0x10000>;
	};
};

&can0 {
	status = "okay";
	pinctrl-names = "default";