Commit e72f8f62 authored by Sung Lee's avatar Sung Lee Committed by Alex Deucher
Browse files

drm/amd/display: Do not call update bounding box on dc create



[Why]
In Hybrid Graphics, dcn2_1_soc struct stays alive through PnP.
This causes an issue on dc init where dcn2_1_soc which has been
updated by update_bw_bounding_box gets put into dml->soc.
As update_bw_bounding_box is currently incorrect for dcn2.1,
this makes dml calculations fail due to incorrect parameters,
leading to a crash on PnP.

[How]
Comment out update_bw_bounding_box call for now.

Signed-off-by: default avatarSung Lee <sung.lee@amd.com>
Reviewed-by: default avatarEric Yang <eric.yang2@amd.com>
Acked-by: default avatarLeo Li <sunpeng.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3b733278
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+7 −1
Original line number Diff line number Diff line
@@ -1336,6 +1336,12 @@ struct display_stream_compressor *dcn21_dsc_create(

static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
{
	/*
	TODO: Fix this function to calcualte correct values.
	There are known issues with this function currently
	that will need to be investigated. Use hardcoded known good values for now.


	struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
	struct clk_limit_table *clk_table = &bw_params->clk_table;
	int i;
@@ -1350,11 +1356,11 @@ static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
		dcn2_1_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
		dcn2_1_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
		dcn2_1_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
		/* This is probably wrong, TODO: find correct calculation */
		dcn2_1_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 16 / 1000;
	}
	dcn2_1_soc.clock_limits[i] = dcn2_1_soc.clock_limits[i - i];
	dcn2_1_soc.num_states = i;
	*/
}

/* Temporary Place holder until we can get them from fuse */