Commit e7289c6d authored by Thomas Gleixner's avatar Thomas Gleixner Committed by Ingo Molnar
Browse files

sched/rt, ARM: Use CONFIG_PREEMPTION 



CONFIG_PREEMPTION is selected by CONFIG_PREEMPT and by CONFIG_PREEMPT_RT.
Both PREEMPT and PREEMPT_RT require the same functionality which today
depends on CONFIG_PREEMPT.

Switch the entry code, cache over to use CONFIG_PREEMPTION and add output
in show_stack() for PREEMPT_RT.

[bigeasy: +traps.c]

Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Signed-off-by: default avatarSebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Russell King <linux@armlinux.org.uk>
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lore.kernel.org/r/20191015191821.11479-2-bigeasy@linutronix.de


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 4f797f56

arch/arm/include/asm/switch_to.h

+1 −1
Original line number Diff line number Diff line
@@ -10,7 +10,7 @@ 
 * to ensure that the maintenance completes in case we migrate to another

 * CPU.

 */

#if defined(CONFIG_PREEMPT) && defined(CONFIG_SMP) && defined(CONFIG_CPU_V7)

#if defined(CONFIG_PREEMPTION) && defined(CONFIG_SMP) && defined(CONFIG_CPU_V7)

#define __complete_pending_tlbi()	dsb(ish)

#else

#define __complete_pending_tlbi()

arch/arm/kernel/entry-armv.S

+2 −2
Original line number Diff line number Diff line
@@ -211,7 +211,7 @@ __irq_svc: 
	svc_entry

	irq_handler



#ifdef CONFIG_PREEMPT

#ifdef CONFIG_PREEMPTION

	ldr	r8, [tsk, #TI_PREEMPT]		@ get preempt count

	ldr	r0, [tsk, #TI_FLAGS]		@ get flags

	teq	r8, #0				@ if preempt count != 0
@@ -226,7 +226,7 @@ ENDPROC(__irq_svc) 


	.ltorg



#ifdef CONFIG_PREEMPT

#ifdef CONFIG_PREEMPTION

svc_preempt:

	mov	r8, lr

1:	bl	preempt_schedule_irq		@ irq en/disable is done inside

arch/arm/kernel/traps.c

+2 −0
Original line number Diff line number Diff line
@@ -248,6 +248,8 @@ void show_stack(struct task_struct *tsk, unsigned long *sp) 


#ifdef CONFIG_PREEMPT

#define S_PREEMPT " PREEMPT"

#elif defined(CONFIG_PREEMPT_RT)

#define S_PREEMPT " PREEMPT_RT"

#else

#define S_PREEMPT ""

#endif

arch/arm/mm/cache-v7.S

+2 −2
Original line number Diff line number Diff line
@@ -135,13 +135,13 @@ flush_levels: 
	and	r1, r1, #7			@ mask of the bits for current cache only

	cmp	r1, #2				@ see what cache we have at this level

	blt	skip				@ skip if no cache, or just i-cache

#ifdef CONFIG_PREEMPT

#ifdef CONFIG_PREEMPTION

	save_and_disable_irqs_notrace r9	@ make cssr&csidr read atomic

#endif

	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr

	isb					@ isb to sych the new cssr&csidr

	mrc	p15, 1, r1, c0, c0, 0		@ read the new csidr

#ifdef CONFIG_PREEMPT

#ifdef CONFIG_PREEMPTION

	restore_irqs_notrace r9

#endif

	and	r2, r1, #7			@ extract the length of the cache lines

arch/arm/mm/cache-v7m.S

+2 −2
Original line number Diff line number Diff line
@@ -183,13 +183,13 @@ flush_levels: 
	and	r1, r1, #7			@ mask of the bits for current cache only

	cmp	r1, #2				@ see what cache we have at this level

	blt	skip				@ skip if no cache, or just i-cache

#ifdef CONFIG_PREEMPT

#ifdef CONFIG_PREEMPTION

	save_and_disable_irqs_notrace r9	@ make cssr&csidr read atomic

#endif

	write_csselr r10, r1			@ set current cache level

	isb					@ isb to sych the new cssr&csidr

	read_ccsidr r1				@ read the new csidr

#ifdef CONFIG_PREEMPT

#ifdef CONFIG_PREEMPTION

	restore_irqs_notrace r9

#endif

	and	r2, r1, #7			@ extract the length of the cache lines

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