Commit e723ff66 authored by David Brownell's avatar David Brownell Committed by Haavard Skinnemoen
Browse files

avr32: Generic clockevents support 



This combines three patches from David Brownell:
  * avr32: tclib support
  * avr32: simplify clocksources
  * avr32: Turn count/compare into a oneshot clockevent device

Register both TC blocks (instead of just the first one) so that
the AT32/AT91 tclib code will pick them up (instead of just the
avr32-only PIT-style clocksource).

Rename the first one and its resources appropriately.

More cleanups to the cycle counter clocksource code

 - Disable all the weak symbol magic; remove the AVR32-only TCB-based
   clocksource code (source and header).

 - Mark the __init code properly.

 - Don't forget to report IRQF_TIMER.

 - Make the system work properly with this clocksource, by preventing
   use of the CPU "idle" sleep state in the idle loop when it's used.

Package the avr32 count/compare timekeeping support as a oneshot
clockevent device, so it supports NO_HZ and high res timers.
This means it also supports plugging in other clockevent devices
and clocksources.

Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: default avatarHaavard Skinnemoen <hskinnemoen@atmel.com>
parent 7e59128f

arch/avr32/Kconfig

+5 −0
Original line number Diff line number Diff line
@@ -47,6 +47,9 @@ config RWSEM_GENERIC_SPINLOCK 
config GENERIC_TIME

	def_bool y



config GENERIC_CLOCKEVENTS

	def_bool y



config RWSEM_XCHGADD_ALGORITHM

	def_bool n
@@ -70,6 +73,8 @@ source "init/Kconfig" 


menu "System Type and features"



source "kernel/time/Kconfig"



config SUBARCH_AVR32B

	bool

config MMU

arch/avr32/kernel/time.c

+80 −129
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2004-2007 Atmel Corporation

 *

 * Based on MIPS implementation arch/mips/kernel/time.c

 *   Copyright 2001 MontaVista Software Inc.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */



#include <linux/clk.h>

#include <linux/clocksource.h>

#include <linux/clockchips.h>

#include <linux/time.h>

#include <linux/module.h>

#include <linux/interrupt.h>
@@ -27,13 +23,10 @@ 
#include <asm/io.h>

#include <asm/sections.h>



/* how many counter cycles in a jiffy? */

static u32 cycles_per_jiffy;

#include <asm/arch/pm.h>



/* the count value for the next timer interrupt */

static u32 expirelo;



cycle_t __weak read_cycle_count(void)

static cycle_t read_cycle_count(void)

{

	return (cycle_t)sysreg_read(COUNT);

}
@@ -42,10 +35,11 @@ cycle_t __weak read_cycle_count(void) 
 * The architectural cycle count registers are a fine clocksource unless

 * the system idle loop use sleep states like "idle":  the CPU cycles

 * measured by COUNT (and COMPARE) don't happen during sleep states.

 * Their duration also changes if cpufreq changes the CPU clock rate.

 * So we rate the clocksource using COUNT as very low quality.

 */

struct clocksource __weak clocksource_avr32 = {

	.name		= "avr32",

static struct clocksource counter = {

	.name		= "avr32_counter",

	.rating		= 50,

	.read		= read_cycle_count,

	.mask		= CLOCKSOURCE_MASK(32),
@@ -53,152 +47,109 @@ struct clocksource __weak clocksource_avr32 = { 
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,

};



irqreturn_t __weak timer_interrupt(int irq, void *dev_id);



struct irqaction timer_irqaction = {

	.handler	= timer_interrupt,

	.flags		= IRQF_DISABLED,

	.name		= "timer",

};



static void avr32_timer_ack(void)

static irqreturn_t timer_interrupt(int irq, void *dev_id)

{

	u32 count;



	/* Ack this timer interrupt and set the next one */

	expirelo += cycles_per_jiffy;

	/* setting COMPARE to 0 stops the COUNT-COMPARE */

	if (expirelo == 0) {

		sysreg_write(COMPARE, expirelo + 1);

	} else {

		sysreg_write(COMPARE, expirelo);

	}

	struct clock_event_device *evdev = dev_id;



	/* Check to see if we have missed any timer interrupts */

	count = sysreg_read(COUNT);

	if ((count - expirelo) < 0x7fffffff) {

		expirelo = count + cycles_per_jiffy;

		sysreg_write(COMPARE, expirelo);

	}

}

	/*

	 * Disable the interrupt until the clockevent subsystem

	 * reprograms it.

	 */

	sysreg_write(COMPARE, 0);



int __weak avr32_hpt_init(void)

{

	int ret;

	unsigned long mult, shift, count_hz;

	evdev->event_handler(evdev);

	return IRQ_HANDLED;

}



	count_hz = clk_get_rate(boot_cpu_data.clk);

	shift = clocksource_avr32.shift;

	mult = clocksource_hz2mult(count_hz, shift);

	clocksource_avr32.mult = mult;

static struct irqaction timer_irqaction = {

	.handler	= timer_interrupt,

	.flags		= IRQF_TIMER | IRQF_DISABLED,

	.name		= "avr32_comparator",

};



static int comparator_next_event(unsigned long delta,

		struct clock_event_device *evdev)

{

		u64 tmp;

	unsigned long	flags;



		tmp = TICK_NSEC;

		tmp <<= shift;

		tmp += mult / 2;

		do_div(tmp, mult);



		cycles_per_jiffy = tmp;

	}

	raw_local_irq_save(flags);



	ret = setup_irq(0, &timer_irqaction);

	if (ret) {

		pr_debug("timer: could not request IRQ 0: %d\n", ret);

		return -ENODEV;

	}

	/* The time to read COUNT then update COMPARE must be less

	 * than the min_delta_ns value for this clockevent source.

	 */

	sysreg_write(COMPARE, (sysreg_read(COUNT) + delta) ? : 1);



	printk(KERN_INFO "timer: AT32AP COUNT-COMPARE at irq 0, "

			"%lu.%03lu MHz\n",

			((count_hz + 500) / 1000) / 1000,

			((count_hz + 500) / 1000) % 1000);

	raw_local_irq_restore(flags);



	return 0;

}



/*

 * Taken from MIPS c0_hpt_timer_init().

 *

 * The reason COUNT is written twice is probably to make sure we don't get any

 * timer interrupts while we are messing with the counter.

 */

int __weak avr32_hpt_start(void)

static void comparator_mode(enum clock_event_mode mode,

		struct clock_event_device *evdev)

{

	u32 count = sysreg_read(COUNT);

	expirelo = (count / cycles_per_jiffy + 1) * cycles_per_jiffy;

	sysreg_write(COUNT, expirelo - cycles_per_jiffy);

	sysreg_write(COMPARE, expirelo);

	sysreg_write(COUNT, count);



	return 0;

	switch (mode) {

	case CLOCK_EVT_MODE_ONESHOT:

		pr_debug("%s: start\n", evdev->name);

		/* FALLTHROUGH */

	case CLOCK_EVT_MODE_RESUME:

		cpu_disable_idle_sleep();

		break;

	case CLOCK_EVT_MODE_UNUSED:

	case CLOCK_EVT_MODE_SHUTDOWN:

		sysreg_write(COMPARE, 0);

		pr_debug("%s: stop\n", evdev->name);

		cpu_enable_idle_sleep();

		break;

	default:

		BUG();

	}



/*

 * local_timer_interrupt() does profiling and process accounting on a

 * per-CPU basis.

 *

 * In UP mode, it is invoked from the (global) timer_interrupt.

 */

void local_timer_interrupt(int irq, void *dev_id)

{

	if (current->pid)

		profile_tick(CPU_PROFILING);

	update_process_times(user_mode(get_irq_regs()));

}



irqreturn_t __weak timer_interrupt(int irq, void *dev_id)

{

	/* ack timer interrupt and try to set next interrupt */

	avr32_timer_ack();



	/*

	 * Call the generic timer interrupt handler

	 */

	write_seqlock(&xtime_lock);

	do_timer(1);

	write_sequnlock(&xtime_lock);



	/*

	 * In UP mode, we call local_timer_interrupt() to do profiling

	 * and process accounting.

	 *

	 * SMP is not supported yet.

	 */

	local_timer_interrupt(irq, dev_id);



	return IRQ_HANDLED;

}

static struct clock_event_device comparator = {

	.name		= "avr32_comparator",

	.features	= CLOCK_EVT_FEAT_ONESHOT,

	.shift		= 16,

	.rating		= 50,

	.cpumask	= CPU_MASK_CPU0,

	.set_next_event	= comparator_next_event,

	.set_mode	= comparator_mode,

};



void __init time_init(void)

{

	unsigned long counter_hz;

	int ret;



	/*

	 * Make sure we don't get any COMPARE interrupts before we can

	 * handle them.

	 */

	sysreg_write(COMPARE, 0);



	xtime.tv_sec = mktime(2007, 1, 1, 0, 0, 0);

	xtime.tv_nsec = 0;



	set_normalized_timespec(&wall_to_monotonic,

				-xtime.tv_sec, -xtime.tv_nsec);



	ret = avr32_hpt_init();

	if (ret) {

		pr_debug("timer: failed setup: %d\n", ret);

		return;

	}

	/* figure rate for counter */

	counter_hz = clk_get_rate(boot_cpu_data.clk);

	counter.mult = clocksource_hz2mult(counter_hz, counter.shift);



	ret = clocksource_register(&clocksource_avr32);

	ret = clocksource_register(&counter);

	if (ret)

		pr_debug("timer: could not register clocksource: %d\n", ret);



	ret = avr32_hpt_start();

	if (ret) {

		pr_debug("timer: failed starting: %d\n", ret);

		return;

	/* setup COMPARE clockevent */

	comparator.mult = div_sc(counter_hz, NSEC_PER_SEC, comparator.shift);

	comparator.max_delta_ns = clockevent_delta2ns((u32)~0, &comparator);

	comparator.min_delta_ns = clockevent_delta2ns(50, &comparator) + 1;



	sysreg_write(COMPARE, 0);

	timer_irqaction.dev_id = &comparator;



	ret = setup_irq(0, &timer_irqaction);

	if (ret)

		pr_debug("timer: could not request IRQ 0: %d\n", ret);

	else {

		clockevents_register_device(&comparator);



		pr_info("%s: irq 0, %lu.%03lu MHz\n", comparator.name,

				((counter_hz + 500) / 1000) / 1000,

				((counter_hz + 500) / 1000) % 1000);

	}

}

arch/avr32/mach-at32ap/Makefile

+0 −1
Original line number Diff line number Diff line 
obj-y				+= at32ap.o clock.o intc.o extint.o pio.o hsmc.o

obj-$(CONFIG_CPU_AT32AP700X)	+= at32ap700x.o pm-at32ap700x.o

obj-$(CONFIG_CPU_AT32AP700X)	+= time-tc.o

obj-$(CONFIG_CPU_FREQ_AT32AP)	+= cpufreq.o

arch/avr32/mach-at32ap/at32ap700x.c

+24 −9
Original line number Diff line number Diff line
@@ -606,19 +606,32 @@ static inline void set_ebi_sfr_bits(u32 mask) 
}



/* --------------------------------------------------------------------

 *  System Timer/Counter (TC)

 *  Timer/Counter (TC)

 * -------------------------------------------------------------------- */

static struct resource at32_systc0_resource[] = {



static struct resource at32_tcb0_resource[] = {

	PBMEM(0xfff00c00),

	IRQ(22),

};

struct platform_device at32_systc0_device = {

	.name		= "systc",

static struct platform_device at32_tcb0_device = {

	.name		= "atmel_tcb",

	.id		= 0,

	.resource	= at32_systc0_resource,

	.num_resources	= ARRAY_SIZE(at32_systc0_resource),

	.resource	= at32_tcb0_resource,

	.num_resources	= ARRAY_SIZE(at32_tcb0_resource),

};

DEV_CLK(t0_clk, at32_tcb0, pbb, 3);



static struct resource at32_tcb1_resource[] = {

	PBMEM(0xfff01000),

	IRQ(23),

};

static struct platform_device at32_tcb1_device = {

	.name		= "atmel_tcb",

	.id		= 1,

	.resource	= at32_tcb1_resource,

	.num_resources	= ARRAY_SIZE(at32_tcb1_resource),

};

DEV_CLK(pclk, at32_systc0, pbb, 3);

DEV_CLK(t0_clk, at32_tcb1, pbb, 4);



/* --------------------------------------------------------------------

 *  PIO
@@ -670,7 +683,8 @@ void __init at32_add_system_devices(void) 
	platform_device_register(&pdc_device);

	platform_device_register(&dmaca0_device);



	platform_device_register(&at32_systc0_device);

	platform_device_register(&at32_tcb0_device);

	platform_device_register(&at32_tcb1_device);



	platform_device_register(&pio0_device);

	platform_device_register(&pio1_device);
@@ -1737,7 +1751,8 @@ struct clk *at32_clock_list[] = { 
	&pio2_mck,

	&pio3_mck,

	&pio4_mck,

	&at32_systc0_pclk,

	&at32_tcb0_t0_clk,

	&at32_tcb1_t0_clk,

	&atmel_usart0_usart,

	&atmel_usart1_usart,

	&atmel_usart2_usart,

arch/avr32/mach-at32ap/time-tc.c

deleted100644 → 0
+0 −218
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2004-2007 Atmel Corporation

 *

 * Based on MIPS implementation arch/mips/kernel/time.c

 *   Copyright 2001 MontaVista Software Inc.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */



#include <linux/clk.h>

#include <linux/clocksource.h>

#include <linux/time.h>

#include <linux/module.h>

#include <linux/interrupt.h>

#include <linux/irq.h>

#include <linux/kernel_stat.h>

#include <linux/errno.h>

#include <linux/init.h>

#include <linux/profile.h>

#include <linux/sysdev.h>

#include <linux/err.h>



#include <asm/div64.h>

#include <asm/sysreg.h>

#include <asm/io.h>

#include <asm/sections.h>



#include <asm/arch/time.h>



/* how many counter cycles in a jiffy? */

static u32 cycles_per_jiffy;



/* the count value for the next timer interrupt */

static u32 expirelo;



/* the I/O registers of the TC module */

static void __iomem *ioregs;



cycle_t read_cycle_count(void)

{

	return (cycle_t)timer_read(ioregs, 0, CV);

}



struct clocksource clocksource_avr32 = {

	.name		= "avr32",

	.rating		= 342,

	.read		= read_cycle_count,

	.mask		= CLOCKSOURCE_MASK(16),

	.shift		= 16,

	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,

};



static void avr32_timer_ack(void)

{

	u16 count = expirelo;



	/* Ack this timer interrupt and set the next one, use a u16

	 * variable so it will wrap around correctly */

	count += cycles_per_jiffy;

	expirelo = count;

	timer_write(ioregs, 0, RC, expirelo);



	/* Check to see if we have missed any timer interrupts */

	count = timer_read(ioregs, 0, CV);

	if ((count - expirelo) < 0x7fff) {

		expirelo = count + cycles_per_jiffy;

		timer_write(ioregs, 0, RC, expirelo);

	}

}



u32 avr32_hpt_read(void)

{

	return timer_read(ioregs, 0, CV);

}



static int avr32_timer_calc_div_and_set_jiffies(struct clk *pclk)

{

	unsigned int cycles_max = (clocksource_avr32.mask + 1) / 2;

	unsigned int divs[] = { 4, 8, 16, 32 };

	int divs_size = ARRAY_SIZE(divs);

	int i = 0;

	unsigned long count_hz;

	unsigned long shift;

	unsigned long mult;

	int clock_div = -1;

	u64 tmp;



	shift = clocksource_avr32.shift;



	do {

		count_hz = clk_get_rate(pclk) / divs[i];

		mult = clocksource_hz2mult(count_hz, shift);

		clocksource_avr32.mult = mult;



		tmp = TICK_NSEC;

		tmp <<= shift;

		tmp += mult / 2;

		do_div(tmp, mult);



		cycles_per_jiffy = tmp;

	} while (cycles_per_jiffy > cycles_max && ++i < divs_size);



	clock_div = i + 1;



	if (clock_div > divs_size) {

		pr_debug("timer: could not calculate clock divider\n");

		return -EFAULT;

	}



	/* Set the clock divider */

	timer_write(ioregs, 0, CMR, TIMER_BF(CMR_TCCLKS, clock_div));



	return 0;

}



int avr32_hpt_init(unsigned int count)

{

	struct resource *regs;

	struct clk *pclk;

	int irq = -1;

	int ret = 0;



	ret = -ENXIO;



	irq = platform_get_irq(&at32_systc0_device, 0);

	if (irq < 0) {

		pr_debug("timer: could not get irq\n");

		goto out_error;

	}



	pclk = clk_get(&at32_systc0_device.dev, "pclk");

	if (IS_ERR(pclk)) {

		pr_debug("timer: could not get clk: %ld\n", PTR_ERR(pclk));

		goto out_error;

	}

	clk_enable(pclk);



	regs = platform_get_resource(&at32_systc0_device, IORESOURCE_MEM, 0);

	if (!regs) {

		pr_debug("timer: could not get resource\n");

		goto out_error_clk;

	}



	ioregs = ioremap(regs->start, regs->end - regs->start + 1);

	if (!ioregs) {

		pr_debug("timer: could not get ioregs\n");

		goto out_error_clk;

	}



	ret = avr32_timer_calc_div_and_set_jiffies(pclk);

	if (ret)

		goto out_error_io;



	ret = setup_irq(irq, &timer_irqaction);

	if (ret) {

		pr_debug("timer: could not request irq %d: %d\n",

				irq, ret);

		goto out_error_io;

	}



	expirelo = (timer_read(ioregs, 0, CV) / cycles_per_jiffy + 1)

		* cycles_per_jiffy;



	/* Enable clock and interrupts on RC compare */

	timer_write(ioregs, 0, CCR, TIMER_BIT(CCR_CLKEN));

	timer_write(ioregs, 0, IER, TIMER_BIT(IER_CPCS));

	/* Set cycles to first interrupt */

	timer_write(ioregs, 0,  RC, expirelo);



	printk(KERN_INFO "timer: AT32AP system timer/counter at 0x%p irq %d\n",

			ioregs, irq);



	return 0;



out_error_io:

	iounmap(ioregs);

out_error_clk:

	clk_put(pclk);

out_error:

	return ret;

}



int avr32_hpt_start(void)

{

	timer_write(ioregs, 0, CCR, TIMER_BIT(CCR_SWTRG));

	return 0;

}



irqreturn_t timer_interrupt(int irq, void *dev_id)

{

	unsigned int sr = timer_read(ioregs, 0, SR);



	if (sr & TIMER_BIT(SR_CPCS)) {

		/* ack timer interrupt and try to set next interrupt */

		avr32_timer_ack();



		/*

		 * Call the generic timer interrupt handler

		 */

		write_seqlock(&xtime_lock);

		do_timer(1);

		write_sequnlock(&xtime_lock);



		/*

		 * In UP mode, we call local_timer_interrupt() to do profiling

		 * and process accounting.

		 *

		 * SMP is not supported yet.

		 */

		local_timer_interrupt(irq, dev_id);



		return IRQ_HANDLED;

	}



	return IRQ_NONE;

}

CRA Git | Maintained and supported by SUSTech CRA and CCSE