Commit e71de076 authored Oct 12, 2017 by pding Committed by Alex Deucher Oct 19, 2017

drm/amdgpu: report more amdgpu_fence_info



Only for GFX ring. This can help checking MCBP feature.

The fence at the end of the frame will indicate the completion status.
If the frame completed normally, the fence is written to the address
given in the EVENT_WRITE_EOP packet. If preemption occurred in the
previous IB the address is adjusted by 2 DWs. If work submitted in the
frame was reset before completion, the fence address is adjusted by
four DWs. In the case that preemption occurred, and before preemption
completed a reset was initiated, the address will be adjusted with six
DWs

Signed-off-by: pding <Pixel.Ding@amd.com>
Reviewed-by: Monk Liu <monk.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent f993d628

drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

+13 −0

Original line number	Diff line number	Diff line
		@@ -641,6 +641,19 @@ static int amdgpu_debugfs_fence_info(struct seq_file m, void data)
		atomic_read(&ring->fence_drv.last_seq));
		seq_printf(m, "Last emitted 0x%08x\n",
		ring->fence_drv.sync_seq);

		if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)
		continue;

		/* set in CP_VMID_PREEMPT and preemption occurred */
		seq_printf(m, "Last preempted 0x%08x\n",
		le32_to_cpu(*(ring->fence_drv.cpu_addr + 2)));
		/* set in CP_VMID_RESET and reset occurred */
		seq_printf(m, "Last reset 0x%08x\n",
		le32_to_cpu(*(ring->fence_drv.cpu_addr + 4)));
		/* Both preemption and reset occurred */
		seq_printf(m, "Last both 0x%08x\n",
		le32_to_cpu(*(ring->fence_drv.cpu_addr + 6)));
		}
		return 0;
		}

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