Commit e7167769 authored by Mika Kuoppala's avatar Mika Kuoppala Committed by Mika Kuoppala
Browse files

drm/i915: Avoid using word legacy with ppgtt 



The term legacy is subjective. Use 3lvl and 4lvl
where appropriate.

Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1488295691-9404-4-git-send-email-mika.kuoppala@intel.com
parent 1e6437b0

drivers/gpu/drm/i915/i915_gem_gtt.c

+8 −10
Original line number Diff line number Diff line
@@ -641,12 +641,12 @@ static int gen8_write_pdp(struct drm_i915_gem_request *req, 
	return 0;

}



static int gen8_legacy_mm_switch(struct i915_hw_ppgtt *ppgtt,

static int gen8_mm_switch_3lvl(struct i915_hw_ppgtt *ppgtt,

			       struct drm_i915_gem_request *req)

{

	int i, ret;



	for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {

	for (i = GEN8_3LVL_PDPES - 1; i >= 0; i--) {

		const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);



		ret = gen8_write_pdp(req, i, pd_daddr);
@@ -657,7 +657,7 @@ static int gen8_legacy_mm_switch(struct i915_hw_ppgtt *ppgtt, 
	return 0;

}



static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,

static int gen8_mm_switch_4lvl(struct i915_hw_ppgtt *ppgtt,

			       struct drm_i915_gem_request *req)

{

	return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4));
@@ -1016,7 +1016,7 @@ static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create) 
		msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE :

				VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY);

	} else {

		for (i = 0; i < GEN8_LEGACY_PDPES; i++) {

		for (i = 0; i < GEN8_3LVL_PDPES; i++) {

			const u64 daddr = i915_page_dir_dma_addr(ppgtt, i);



			I915_WRITE(vgtif_reg(pdp[i].lo), lower_32_bits(daddr));
@@ -1356,8 +1356,7 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) 


		gen8_initialize_pml4(&ppgtt->base, &ppgtt->pml4);



		ppgtt->switch_mm = gen8_48b_mm_switch;



		ppgtt->switch_mm = gen8_mm_switch_4lvl;

		ppgtt->base.allocate_va_range = gen8_ppgtt_alloc_4lvl;

		ppgtt->base.insert_entries = gen8_ppgtt_insert_4lvl;

		ppgtt->base.clear_range = gen8_ppgtt_clear_4lvl;
@@ -1366,8 +1365,6 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) 
		if (ret)

			goto free_scratch;



		ppgtt->switch_mm = gen8_legacy_mm_switch;



		if (intel_vgpu_active(dev_priv)) {

			ret = gen8_preallocate_top_level_pdp(ppgtt);

			if (ret) {
@@ -1376,6 +1373,7 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) 
			}

		}



		ppgtt->switch_mm = gen8_mm_switch_3lvl;

		ppgtt->base.allocate_va_range = gen8_ppgtt_alloc_3lvl;

		ppgtt->base.insert_entries = gen8_ppgtt_insert_3lvl;

		ppgtt->base.clear_range = gen8_ppgtt_clear_3lvl;

drivers/gpu/drm/i915/i915_gem_gtt.h

+11 −10
Original line number Diff line number Diff line
@@ -101,13 +101,20 @@ typedef u64 gen8_ppgtt_pml4e_t; 
#define HSW_GTT_ADDR_ENCODE(addr)	((addr) | (((addr) >> 28) & 0x7f0))

#define HSW_PTE_ADDR_ENCODE(addr)	HSW_GTT_ADDR_ENCODE(addr)



/* GEN8 legacy style address is defined as a 3 level page table:

/* GEN8 32b style address is defined as a 3 level page table:

 * 31:30 | 29:21 | 20:12 |  11:0

 * PDPE  |  PDE  |  PTE  | offset

 * The difference as compared to normal x86 3 level page table is the PDPEs are

 * programmed via register.

 *

 * GEN8 48b legacy style address is defined as a 4 level page table:

 */

#define GEN8_3LVL_PDPES			4

#define GEN8_PDE_SHIFT			21

#define GEN8_PDE_MASK			0x1ff

#define GEN8_PTE_SHIFT			12

#define GEN8_PTE_MASK			0x1ff

#define GEN8_PTES			I915_PTES(sizeof(gen8_pte_t))



/* GEN8 48b style address is defined as a 4 level page table:

 * 47:39 | 38:30 | 29:21 | 20:12 |  11:0

 * PML4E | PDPE  |  PDE  |  PTE  | offset

 */
@@ -118,12 +125,6 @@ typedef u64 gen8_ppgtt_pml4e_t; 
/* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page

 * tables */

#define GEN8_PDPE_MASK			0x1ff

#define GEN8_PDE_SHIFT			21

#define GEN8_PDE_MASK			0x1ff

#define GEN8_PTE_SHIFT			12

#define GEN8_PTE_MASK			0x1ff

#define GEN8_LEGACY_PDPES		4

#define GEN8_PTES			I915_PTES(sizeof(gen8_pte_t))



#define PPAT_UNCACHED_INDEX		(_PAGE_PWT | _PAGE_PCD)

#define PPAT_CACHED_PDE_INDEX		0 /* WB LLC */
@@ -466,7 +467,7 @@ i915_pdpes_per_pdp(const struct i915_address_space *vm) 
	if (i915_vm_is_48bit(vm))

		return GEN8_PML4ES_PER_PML4;



	return GEN8_LEGACY_PDPES;

	return GEN8_3LVL_PDPES;

}



/* Equivalent to the gen6 version, For each pde iterates over every pde

drivers/gpu/drm/i915/intel_lrc.c

+2 −2
Original line number Diff line number Diff line
@@ -1265,7 +1265,7 @@ static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req) 
{

	struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;

	struct intel_engine_cs *engine = req->engine;

	const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;

	const int num_lri_cmds = GEN8_3LVL_PDPES * 2;

	u32 *cs;

	int i;
@@ -1274,7 +1274,7 @@ static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req) 
		return PTR_ERR(cs);



	*cs++ = MI_LOAD_REGISTER_IMM(num_lri_cmds);

	for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {

	for (i = GEN8_3LVL_PDPES - 1; i >= 0; i--) {

		const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);



		*cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i));

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