Commit e6dc10f2 authored by Faiz Abbas's avatar Faiz Abbas Committed by Tero Kristo
Browse files

arm64: dts: ti: j721e-main: Add SDHCI nodes 



Add nodes for the 3 SDHCI instances present on TI's J721E device.
instance 0 supports HS400 (8 bit bus widht, DDR, 400 MBps)
while instances 1 and 2 support SDR104 (4 bit width, SDR, 100 MBps) as
their highest speed modes. Currently, only High speed (50 MHz clock) has
been enabled.

Signed-off-by: default avatarFaiz Abbas <faiz_abbas@ti.com>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
parent eb9f9173

arch/arm64/boot/dts/ti/k3-j721e-main.dtsi

+50 −0
Original line number Diff line number Diff line
@@ -486,4 +486,54 @@ 
		clocks = <&k3_clks 112 0>;

		clock-names = "gpio";

	};



	main_sdhci0: sdhci@4f80000 {

		compatible = "ti,j721e-sdhci-8bit";

		reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;

		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;

		power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;

		clock-names = "clk_xin", "clk_ahb";

		clocks = <&k3_clks 91 1>, <&k3_clks 91 0>;

		assigned-clocks = <&k3_clks 91 1>;

		assigned-clock-parents = <&k3_clks 91 2>;

		bus-width = <8>;

		mmc-hs400-1_8v;

		mmc-ddr-1_8v;

		ti,otap-del-sel = <0x2>;

		ti,trm-icp = <0x8>;

		ti,strobe-sel = <0x77>;

		dma-coherent;

	};



	main_sdhci1: sdhci@4fb0000 {

		compatible = "ti,j721e-sdhci-4bit";

		reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;

		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;

		power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;

		clock-names = "clk_xin", "clk_ahb";

		clocks = <&k3_clks 92 0>, <&k3_clks 92 5>;

		assigned-clocks = <&k3_clks 92 0>;

		assigned-clock-parents = <&k3_clks 92 1>;

		ti,otap-del-sel = <0x2>;

		ti,trm-icp = <0x8>;

		ti,clkbuf-sel = <0x7>;

		dma-coherent;

		no-1-8-v;

	};



	main_sdhci2: sdhci@4f98000 {

		compatible = "ti,j721e-sdhci-4bit";

		reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;

		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;

		power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;

		clock-names = "clk_xin", "clk_ahb";

		clocks = <&k3_clks 93 0>, <&k3_clks 93 5>;

		assigned-clocks = <&k3_clks 93 0>;

		assigned-clock-parents = <&k3_clks 93 1>;

		ti,otap-del-sel = <0x2>;

		ti,trm-icp = <0x8>;

		ti,clkbuf-sel = <0x7>;

		dma-coherent;

		no-1-8-v;

	};

};

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