drm/i915/dp: don't call the link parameters sink parameters (e6c0c64a) · Commits · 戴 / test

drivers/gpu/drm/i915/intel_dp.c

+12 −13

Original line number	Diff line number	Diff line
		@@ -172,7 +172,7 @@ static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
		u8 source_max, sink_max;

		source_max = intel_dig_port->max_lanes;
		sink_max = intel_dp->max_sink_lane_count;
		sink_max = intel_dp->max_link_lane_count;

		return min(source_max, sink_max);
		}
		@@ -326,11 +326,11 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
		intel_dp->num_common_rates,
		link_rate);
		if (index > 0) {
		intel_dp->max_sink_link_rate = intel_dp->common_rates[index - 1];
		intel_dp->max_sink_lane_count = lane_count;
		intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
		intel_dp->max_link_lane_count = lane_count;
		} else if (lane_count > 1) {
		intel_dp->max_sink_link_rate = intel_dp_max_sink_rate(intel_dp);
		intel_dp->max_sink_lane_count = lane_count >> 1;
		intel_dp->max_link_rate = intel_dp_max_sink_rate(intel_dp);
		intel_dp->max_link_lane_count = lane_count >> 1;
		} else {
		DRM_ERROR("Link Training Unsuccessful\n");
		return -1;
		@@ -1561,8 +1561,7 @@ intel_dp_max_link_rate(struct intel_dp *intel_dp)
		{
		int len;

		len = intel_dp_common_len_rate_limit(intel_dp,
		intel_dp->max_sink_link_rate);
		len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
		if (WARN_ON(len <= 0))
		return 162000;

		@@ -1639,7 +1638,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
		uint8_t link_bw, rate_select;

		common_len = intel_dp_common_len_rate_limit(intel_dp,
		intel_dp->max_sink_link_rate);
		intel_dp->max_link_rate);

		/* No common link rates between source and sink */
		WARN_ON(common_len <= 0);
		@@ -3969,7 +3968,7 @@ static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
		test_lane_count &= DP_MAX_LANE_COUNT_MASK;
		/* Validate the requested lane count */
		if (test_lane_count < min_lane_count \|\|
		test_lane_count > intel_dp->max_sink_lane_count)
		test_lane_count > intel_dp->max_link_lane_count)
		return DP_TEST_NAK;

		status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
		@@ -4637,11 +4636,11 @@ intel_dp_long_pulse(struct intel_connector *intel_connector)
		yesno(drm_dp_tps3_supported(intel_dp->dpcd)));

		if (intel_dp->reset_link_params) {
		/* Set the max lane count for sink */
		intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
		/* Set the max lane count for link */
		intel_dp->max_link_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);

		/* Set the max link rate for sink */
		intel_dp->max_sink_link_rate = intel_dp_max_sink_rate(intel_dp);
		/* Set the max link rate for link */
		intel_dp->max_link_rate = intel_dp_max_sink_rate(intel_dp);

		intel_dp->reset_link_params = false;
		}

drivers/gpu/drm/i915/intel_drv.h

+4 −4

Original line number	Diff line number	Diff line
		@@ -959,10 +959,10 @@ struct intel_dp {
		/* intersection of source and sink rates */
		int num_common_rates;
		int common_rates[DP_MAX_SUPPORTED_RATES];
		/* Max lane count for the sink as per DPCD registers */
		uint8_t max_sink_lane_count;
		/* Max link BW for the sink as per DPCD registers */
		int max_sink_link_rate;
		/* Max lane count for the current link */
		int max_link_lane_count;
		/* Max rate for the current link */
		int max_link_rate;
		/* sink or branch descriptor */
		struct intel_dp_desc desc;
		struct drm_dp_aux aux;

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