Commit e6c037bf authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'phy-for-4.7' of... 

Merge tag 'phy-for-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy

 into usb-testing

Kishon writes:

phy: for 4.7

*) Add a new PHY driver for USB2 PHY on Northstar SoC
*) Add support for Broadcom NS2 SATA3 PHY in existing
   Broadcom SATA3 PHY driver
*) Add support for MIPI DPHYs in Exynos5420-compatible
   (5420, 5422 and 5800) and Exynos5433 SoCs
*) Add support for USB3 PHY on mt2701
*) Add extcon support for Renesas R-car USB2 PHY driver
*) Misc cleanups

Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
parents 681fef83 71f5c63c

Documentation/devicetree/bindings/phy/bcm-ns-usb2-phy.txt

0 → 100644
+21 −0
Original line number Diff line number Diff line 
Driver for Broadcom Northstar USB 2.0 PHY



Required properties:

- compatible: brcm,ns-usb2-phy

- reg: iomem address range of DMU (Device Management Unit)

- reg-names: "dmu", the only needed & supported reg right now

- clocks: USB PHY reference clock

- clock-names: "phy-ref-clk", the only needed & supported clock right now



To initialize USB 2.0 PHY driver needs to setup PLL correctly. To do this it

requires passing phandle to the USB PHY reference clock.



Example:

	usb2-phy {

		compatible = "brcm,ns-usb2-phy";

		reg = <0x1800c000 0x1000>;

		reg-names = "dmu";

		#phy-cells = <0>;

		clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;

		clock-names = "phy-ref-clk";

	};

Documentation/devicetree/bindings/phy/brcm,brcmstb-sata-phy.txt→Documentation/devicetree/bindings/phy/brcm-sata-phy.txt

+9 −6
Original line number Diff line number Diff line 
* Broadcom SATA3 PHY for STB

* Broadcom SATA3 PHY



Required properties:

- compatible: should be one or more of

     "brcm,bcm7425-sata-phy"

     "brcm,bcm7445-sata-phy"

     "brcm,iproc-ns2-sata-phy"

     "brcm,phy-sata3"

- address-cells: should be 1

- size-cells: should be 0

- reg: register range for the PHY PCB interface

- reg-names: should be "phy"

- reg: register ranges for the PHY PCB interface

- reg-names: should be "phy" and "phy-ctrl"

     The "phy-ctrl" registers are only required for

     "brcm,iproc-ns2-sata-phy".



Sub-nodes:

  Each port's PHY should be represented as a sub-node.
@@ -16,12 +19,12 @@ Sub-nodes: 
Sub-nodes required properties:

- reg: the PHY number

- phy-cells: generic PHY binding; must be 0

Optional:

- brcm,enable-ssc: use spread spectrum clocking (SSC) on this port



Sub-nodes optional properties:

- brcm,enable-ssc: use spread spectrum clocking (SSC) on this port

     This property is not applicable for "brcm,iproc-ns2-sata-phy".



Example:



	sata-phy@f0458100 {

		compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3";

		reg = <0xf0458100 0x1e00>, <0xf045804c 0x10>;

Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt

+3 −1
Original line number Diff line number Diff line
@@ -4,7 +4,9 @@ mt65xx USB3.0 PHY binding 
This binding describes a usb3.0 phy for mt65xx platforms of Medaitek SoC.



Required properties (controller (parent) node):

 - compatible	: should be "mediatek,mt8173-u3phy"

 - compatible	: should be one of

		  "mediatek,mt2701-u3phy"

		  "mediatek,mt8173-u3phy"

 - reg		: offset and length of register for phy, exclude port's

		  register.

 - clocks	: a list of phandle + clock-specifier pairs, one for each

Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt

+7 −1
Original line number Diff line number Diff line
@@ -7,6 +7,12 @@ Required properties: 
- compatible: "renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC.

	      "renesas,usb-phy-r8a7791" if the device is a part of R8A7791 SoC.

	      "renesas,usb-phy-r8a7794" if the device is a part of R8A7794 SoC.

	      "renesas,rcar-gen2-usb-phy" for a generic R-Car Gen2 compatible device.



	      When compatible with the generic version, nodes must list the

	      SoC-specific version corresponding to the platform first

	      followed by the generic version.



- reg: offset and length of the register block.

- #address-cells: number of address cells for the USB channel subnodes, must

		  be <1>.
@@ -34,7 +40,7 @@ the USB channel; see the selector meanings below: 
Example (Lager board):



	usb-phy@e6590100 {

		compatible = "renesas,usb-phy-r8a7790";

		compatible = "renesas,usb-phy-r8a7790", "renesas,rcar-gen2-usb-phy";

		reg = <0 0xe6590100 0 0x100>;

		#address-cells = <1>;

		#size-cells = <0>;

Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt

+10 −2
Original line number Diff line number Diff line
@@ -6,6 +6,12 @@ This file provides information on what the device node for the R-Car generation 
Required properties:

- compatible: "renesas,usb2-phy-r8a7795" if the device is a part of an R8A7795

	      SoC.

	      "renesas,rcar-gen3-usb2-phy" for a generic R-Car Gen3 compatible device.



	      When compatible with the generic version, nodes must list the

	      SoC-specific version corresponding to the platform first

	      followed by the generic version.



- reg: offset and length of the partial USB 2.0 Host register block.

- clocks: clock phandle and specifier pair(s).

- #phy-cells: see phy-bindings.txt in the same directory, must be <0>.
@@ -15,18 +21,20 @@ To use a USB channel where USB 2.0 Host and HSUSB (USB 2.0 Peripheral) are 
combined, the device tree node should set interrupt properties to use the

channel as USB OTG:

- interrupts: interrupt specifier for the PHY.

- vbus-supply: Phandle to a regulator that provides power to the VBUS. This

	       regulator will be managed during the PHY power on/off sequence.



Example (R-Car H3):



	usb-phy@ee080200 {

		compatible = "renesas,usb2-phy-r8a7795";

		compatible = "renesas,usb2-phy-r8a7795", "renesas,rcar-gen3-usb2-phy";

		reg = <0 0xee080200 0 0x700>;

		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp7_clks R8A7795_CLK_EHCI0>;

	};



	usb-phy@ee0a0200 {

		compatible = "renesas,usb2-phy-r8a7795";

		compatible = "renesas,usb2-phy-r8a7795", "renesas,rcar-gen3-usb2-phy";

		reg = <0 0xee0a0200 0 0x700>;

		clocks = <&mstp7_clks R8A7795_CLK_EHCI0>;

	};

CRA Git | Maintained and supported by SUSTech CRA and CCSE