Commit e6b7b7d8 authored by Potnuri Bharat Teja's avatar Potnuri Bharat Teja Committed by Jason Gunthorpe
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iw_cxgb4: Check for send WR also while posting write with completion WR 



Inorder to optimize the NVMEoF read IOPs, iw_cxgb4 posts a FW Write with
Completion WQE that combines an RDMA Write WR and the subsequent RDMA Send
with Invalidate WR.

This patch is an extension to it, where it posts a Write with completion
for RDMA WRITE WR + RDMA SEND WR combination as well.

Reviewed-by: default avatarSteve Wise <swise@opengridcomputing.com>
Signed-off-by: default avatarPotnuri Bharat Teja <bharat@chelsio.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@mellanox.com>
parent 5aad26a7

drivers/infiniband/hw/cxgb4/qp.c

+13 −6
Original line number Diff line number Diff line
@@ -632,6 +632,9 @@ static void build_rdma_write_cmpl(struct t4_sq *sq, 


	wcwr->stag_sink = cpu_to_be32(rdma_wr(wr)->rkey);

	wcwr->to_sink = cpu_to_be64(rdma_wr(wr)->remote_addr);

	if (wr->next->opcode == IB_WR_SEND)

		wcwr->stag_inv = 0;

	else

		wcwr->stag_inv = cpu_to_be32(wr->next->ex.invalidate_rkey);

	wcwr->r2 = 0;

	wcwr->r3 = 0;
@@ -726,6 +729,9 @@ static void post_write_cmpl(struct c4iw_qp *qhp, const struct ib_send_wr *wr) 


	/* SEND_WITH_INV swsqe */

	swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];

	if (wr->next->opcode == IB_WR_SEND)

		swsqe->opcode = FW_RI_SEND;

	else

		swsqe->opcode = FW_RI_SEND_WITH_INV;

	swsqe->idx = qhp->wq.sq.pidx;

	swsqe->complete = 0;
@@ -1133,9 +1139,9 @@ int c4iw_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 
	/*

	 * Fastpath for NVMe-oF target WRITE + SEND_WITH_INV wr chain which is

	 * the response for small NVMEe-oF READ requests.  If the chain is

	 * exactly a WRITE->SEND_WITH_INV and the sgl depths and lengths

	 * meet the requirements of the fw_ri_write_cmpl_wr work request,

	 * then build and post the write_cmpl WR.  If any of the tests

	 * exactly a WRITE->SEND_WITH_INV or a WRITE->SEND and the sgl depths

	 * and lengths meet the requirements of the fw_ri_write_cmpl_wr work

	 * request, then build and post the write_cmpl WR. If any of the tests

	 * below are not true, then we continue on with the tradtional WRITE

	 * and SEND WRs.

	 */
@@ -1145,7 +1151,8 @@ int c4iw_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 
	    wr && wr->next && !wr->next->next &&

	    wr->opcode == IB_WR_RDMA_WRITE &&

	    wr->sg_list[0].length && wr->num_sge <= T4_WRITE_CMPL_MAX_SGL &&

	    wr->next->opcode == IB_WR_SEND_WITH_INV &&

	    (wr->next->opcode == IB_WR_SEND ||

	    wr->next->opcode == IB_WR_SEND_WITH_INV) &&

	    wr->next->sg_list[0].length == T4_WRITE_CMPL_MAX_CQE &&

	    wr->next->num_sge == 1 && num_wrs >= 2) {

		post_write_cmpl(qhp, wr);

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