Commit e6508c7e authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'phy-for-5.4' of... 

Merge tag 'phy-for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy

 into char-misc-next

Kishon writes:

phy: for 5.4

  *) Add a new PHY driver for Lantiq VRX200/ARX300 PCIe PHY
  *) Add missing of_node_put() to a bunch of drivers using
     for_each_available_child_of_node()
  *) Add RXAUI/PCIe/SATA/USB3 support in Marvell's Armada
     CP110 COMPHY
  *) Other misc fixes and cleanup

Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>

* tag 'phy-for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy: (30 commits)
  phy: marvell: phy-mvebu-cp110-comphy: rename instances of DLT
  phy: marvell: phy-mvebu-cp110-comphy: implement RXAUI support
  dt-bindings: pci: add PHY properties to Armada 7K/8K controller bindings
  dt-bindings: phy: Add Marvell COMPHY clocks
  phy: mvebu-cp110-comphy: Update comment about powering off all lanes at boot
  phy: mvebu-cp110-comphy: Add PCIe support
  phy: mvebu-cp110-comphy: Cosmetic change in a helper
  phy: mvebu-cp110-comphy: Add SATA support
  phy: mvebu-cp110-comphy: Add USB3 host/device support
  phy: mvebu-cp110-comphy: Allow non-Ethernet modes to be configured
  phy: mvebu-cp110-comphy: Rename the macro handling only Ethernet modes
  phy: mvebu-cp110-comphy: Add RXAUI support
  phy: mvebu-cp110-comphy: List already supported Ethernet modes
  phy: mvebu-cp110-comphy: Add SMC call support
  phy: mvebu-cp110-comphy: Explicitly initialize the lane submode
  phy: mvebu-cp110-comphy: Add clocks support
  phy-rockchip-inno-hdmi: Fix RK3328_TERM_RESISTOR_CALIB_SPEED_7_0's third value
  phy: qcom-qmp: Correct ready status, again
  phy: qualcomm: phy-qcom-qmp: Add of_node_put() before return
  phy: renesas: rcar-gen3-usb2: Disable clearing VBUS in over-current
  ...
parents 4a79ce74 5af67635

Documentation/devicetree/bindings/pci/pci-armada8k.txt

+8 −0
Original line number Original line Diff line number Diff line
@@ -17,6 +17,14 @@ Required properties: 
   name must be "core" for the first clock and "reg" for the second

   name must be "core" for the first clock and "reg" for the second

   one

   one





Optional properties:

- phys: phandle(s) to PHY node(s) following the generic PHY bindings.

	Either 1, 2 or 4 PHYs might be needed depending on the number of

	PCIe lanes.

- phy-names: names of the PHYs corresponding to the number of lanes.

	Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for

	2 PHYs.



Example:

Example:





	pcie@f2600000 {

	pcie@f2600000 {

Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml

0 → 100644
+95 −0
Original line number Original line Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Lantiq VRX200 and ARX300 PCIe PHY Device Tree Bindings



maintainers:

  - Martin Blumenstingl <martin.blumenstingl@googlemail.com>



properties:

  "#phy-cells":

    const: 1

    description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>



  compatible:

    enum:

      - lantiq,vrx200-pcie-phy

      - lantiq,arx300-pcie-phy



  reg:

    maxItems: 1



  clocks:

    items:

      - description: PHY module clock

      - description: PDI register clock



  clock-names:

    items:

      - const: phy

      - const: pdi



  resets:

    items:

      - description: exclusive PHY reset line

      - description: shared reset line between the PCIe PHY and PCIe controller



  resets-names:

    items:

      - const: phy

      - const: pcie



  lantiq,rcu:

    $ref: /schemas/types.yaml#/definitions/phandle

    description: phandle to the RCU syscon



  lantiq,rcu-endian-offset:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: the offset of the endian registers for this PHY instance in the RCU syscon



  lantiq,rcu-big-endian-mask:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: the mask to set the PDI (PHY) registers for this PHY instance to big endian



  big-endian:

    description: Configures the PDI (PHY) registers in big-endian mode

    type: boolean



  little-endian:

    description: Configures the PDI (PHY) registers in big-endian mode

    type: boolean



required:

  - "#phy-cells"

  - compatible

  - reg

  - clocks

  - clock-names

  - resets

  - reset-names

  - lantiq,rcu

  - lantiq,rcu-endian-offset

  - lantiq,rcu-big-endian-mask



additionalProperties: false



examples:

  - |

    pcie0_phy: phy@106800 {

        compatible = "lantiq,vrx200-pcie-phy";

        reg = <0x106800 0x100>;

        lantiq,rcu = <&rcu0>;

        lantiq,rcu-endian-offset = <0x4c>;

        lantiq,rcu-big-endian-mask = <0x80>; /* bit 7 */

        big-endian;

        clocks = <&pmu 32>, <&pmu 36>;

        clock-names = "phy", "pdi";

        resets = <&reset0 12 24>, <&reset0 22 22>;

        reset-names = "phy", "pcie";

        #phy-cells = <1>;

    };



...

Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt

+10 −0
Original line number Original line Diff line number Diff line
@@ -25,6 +25,13 @@ Required properties: 
- #address-cells: should be 1.

- #address-cells: should be 1.

- #size-cells: should be 0.

- #size-cells: should be 0.





Optional properlties:



- clocks: pointers to the reference clocks for this device (CP110 only),

          consequently: MG clock, MG Core clock, AXI clock.

- clock-names: names of used clocks for CP110 only, must be :

               "mg_clk", "mg_core_clk" and "axi_clk".



A sub-node is required for each comphy lane provided by the comphy.

A sub-node is required for each comphy lane provided by the comphy.





Required properties (child nodes):

Required properties (child nodes):
@@ -39,6 +46,9 @@ Examples: 
		compatible = "marvell,comphy-cp110";

		compatible = "marvell,comphy-cp110";

		reg = <0x120000 0x6000>;

		reg = <0x120000 0x6000>;

		marvell,system-controller = <&cpm_syscon0>;

		marvell,system-controller = <&cpm_syscon0>;

		clocks = <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,

			 <&CP110_LABEL(clk) 1 18>;

		clock-names = "mg_clk", "mg_core_clk", "axi_clk";

		#address-cells = <1>;

		#address-cells = <1>;

		#size-cells = <0>;

		#size-cells = <0>;

drivers/phy/Makefile

+1 −1
Original line number Original line Diff line number Diff line
@@ -10,7 +10,6 @@ obj-$(CONFIG_PHY_XGENE) += phy-xgene.o 
obj-$(CONFIG_PHY_PISTACHIO_USB)		+= phy-pistachio-usb.o

obj-$(CONFIG_PHY_PISTACHIO_USB)		+= phy-pistachio-usb.o

obj-$(CONFIG_ARCH_SUNXI)		+= allwinner/

obj-$(CONFIG_ARCH_SUNXI)		+= allwinner/

obj-$(CONFIG_ARCH_MESON)		+= amlogic/

obj-$(CONFIG_ARCH_MESON)		+= amlogic/

obj-$(CONFIG_LANTIQ)			+= lantiq/

obj-$(CONFIG_ARCH_MEDIATEK)		+= mediatek/

obj-$(CONFIG_ARCH_MEDIATEK)		+= mediatek/

obj-$(CONFIG_ARCH_RENESAS)		+= renesas/

obj-$(CONFIG_ARCH_RENESAS)		+= renesas/

obj-$(CONFIG_ARCH_ROCKCHIP)		+= rockchip/

obj-$(CONFIG_ARCH_ROCKCHIP)		+= rockchip/
@@ -19,6 +18,7 @@ obj-y += broadcom/ \ 
					   cadence/	\

					   cadence/	\

					   freescale/	\

					   freescale/	\

					   hisilicon/	\

					   hisilicon/	\

					   lantiq/	\

					   marvell/	\

					   marvell/	\

					   motorola/	\

					   motorola/	\

					   mscc/	\

					   mscc/	\

drivers/phy/lantiq/Kconfig

+11 −0
Original line number Original line Diff line number Diff line
@@ -2,6 +2,17 @@ 
#

#

# Phy drivers for Lantiq / Intel platforms

# Phy drivers for Lantiq / Intel platforms

#

#

config PHY_LANTIQ_VRX200_PCIE

	tristate "Lantiq VRX200/ARX300 PCIe PHY"

	depends on SOC_TYPE_XWAY || COMPILE_TEST

	depends on OF && HAS_IOMEM

	select GENERIC_PHY

	select REGMAP_MMIO

	help

	  Support for the PCIe PHY(s) on the Lantiq / Intel VRX200 and ARX300

	  family SoCs.

	  If unsure, say N.



config PHY_LANTIQ_RCU_USB2

config PHY_LANTIQ_RCU_USB2

	tristate "Lantiq XWAY SoC RCU based USB PHY"

	tristate "Lantiq XWAY SoC RCU based USB PHY"

	depends on OF && (SOC_TYPE_XWAY || COMPILE_TEST)

	depends on OF && (SOC_TYPE_XWAY || COMPILE_TEST)

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